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Pipeline 1.5bit DAC offset tolerance

yefj

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Hello, i have shown bellow the relation between Vin and vout in a 1.5bit pipelie adc.
I cant visualise with this pipeline has 1/4*vr offset tollerance?
Thanks.

1594411933599.png
1594411992118.png
1594412084510.png
 

sutapanaki

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Because if you take for example the fist range -Vr to -Vr/4 and you imagine that the bottom comparator has a positive offset of Vr/4, it will flip when the input voltage reaches 0V. Then Vout=0+Vr = Vr. In other words the output of the stage reaches the FSR of the next stage. If offset were to be more than Vr/4 the output will be more than Vr and will overload the next stage.
Similarly, if the top comparator has, for ex. a negative offset of Vr/4, it will flip when Vin=0 and from the 3rd expression Vout=-Vr, i.e. it will be at the negative FSR of the next stage.
 

yefj

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I am looking at this in a simpler manner.
Suppose we wanted to input 0.375 to get 10 logic but because of an error 0.25 error we got it to input 0.125.
so at the output we have 0.125*2=0.25 whichis in the boundary between the two areas but suppose it will pick the 10 logic.

suppose we have an error of 0.25+0.125=0.375 so if my input is 0.375 then it will enter 0 and will stay in that logic level becase 2*0=0 .

But how can i see the exact value of the allowed error?
Thanks.
 

Chinmaye

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I am looking at this in a simpler manner.
Suppose we wanted to input 0.375 to get 10 logic but because of an error 0.25 error we got it to input 0.125.
so at the output we have 0.125*2=0.25 whichis in the boundary between the two areas but suppose it will pick the 10 logic.

suppose we have an error of 0.25+0.125=0.375 so if my input is 0.375 then it will enter 0 and will stay in that logic level becase 2*0=0 .

But how can i see the exact value of the allowed error?
Thanks.
The offset error in the current stage is corrected by the succeeding stages due to the redundancy.
 

sutapanaki

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The offset error is corrected only if it is within +/- Vr/4
 

yefj

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Hello,I have bellow an example which i analised as shown bellow.
How can i see what is the tollerable offset in this example?
Thanks.
1595087757049.png
1595087869598.png
 

yefj

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Hello, i have analized the circuit in fulle extent as shown bellow.
I know that i showed imagine two stage back to back and see "which input could handle both "
Could you please shown how exactly i get this tollerable offset from this case?
Thanks.
1.JPG
2.JPG
1595087869598.png
 

yefj

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Hello, there is a material about 1.5 bit pipe line converters ability to fix errors(till certain point)
I cant find any video lecture which goes in fine detail to explain how it works
If someone could help with that? i looked in al possile video lectures found pipe line in general but NONE about how the fixing error works.


1597089802266.png
 
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danadakk

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Maybe this might help -






Regards, Dana.
 

yefj

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IN this video lecture she promises to explain this phenimena,but in the paylist next lecture is PLL
So the next lecture is measing.

I have found thse links, Ithere is no single example of tolerrable offset in pipeline ADC
 
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sutapanaki

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I can't help you with video lectures on this although I'd watch happily if someone provides a link.
As for the so called digital error correction in pipelined ADCs, the basic idea is that if you can measure the error, you can correct it. That means that if there is an error in one of the piplene stages because of comparator offset, this error can be measured by the backend stages of the pipeline as long as the error doesn't cause the residue go outside the full scale range of the next stage. If it goes outside, then the next stage clips and you can no longer measure the error, hence you can not correct for it.
 
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