# Pipeline 1.5bit DAC offset tolerance

#### yefj #### sutapanaki Because if you take for example the fist range -Vr to -Vr/4 and you imagine that the bottom comparator has a positive offset of Vr/4, it will flip when the input voltage reaches 0V. Then Vout=0+Vr = Vr. In other words the output of the stage reaches the FSR of the next stage. If offset were to be more than Vr/4 the output will be more than Vr and will overload the next stage.
Similarly, if the top comparator has, for ex. a negative offset of Vr/4, it will flip when Vin=0 and from the 3rd expression Vout=-Vr, i.e. it will be at the negative FSR of the next stage.

#### yefj I am looking at this in a simpler manner.
Suppose we wanted to input 0.375 to get 10 logic but because of an error 0.25 error we got it to input 0.125.
so at the output we have 0.125*2=0.25 whichis in the boundary between the two areas but suppose it will pick the 10 logic.

suppose we have an error of 0.25+0.125=0.375 so if my input is 0.375 then it will enter 0 and will stay in that logic level becase 2*0=0 .

But how can i see the exact value of the allowed error?
Thanks.

#### Chinmaye I am looking at this in a simpler manner.
Suppose we wanted to input 0.375 to get 10 logic but because of an error 0.25 error we got it to input 0.125.
so at the output we have 0.125*2=0.25 whichis in the boundary between the two areas but suppose it will pick the 10 logic.

suppose we have an error of 0.25+0.125=0.375 so if my input is 0.375 then it will enter 0 and will stay in that logic level becase 2*0=0 .

But how can i see the exact value of the allowed error?
Thanks.
The offset error in the current stage is corrected by the succeeding stages due to the redundancy.

#### sutapanaki The offset error is corrected only if it is within +/- Vr/4

#### yefj 