Pipe line insertion between fifos

[d4red]

Does anyone have pipe line design example to insert one clock stage between two fifos? If you can share a script, that would be great help.

 

[andre_luis]

Does anyone have pipe line design example to insert one clock stage between two fifos?

Presuming you are solely asking for Pipeline and already have an implementation for the FIFO´s, this task could not be achieved by just adding an useless FIFO ( sized for 1 Flip Flop ) between these other FIFO´s ?



+++

 

[d4red]

Hmm... that's smart solution. I just need to do a little tune up on the one depth fifo, since the data needs some operations. Thanks.

 

[OhaAmo]

As andre told, just add FFs sampling stage (won't necessarily have to be as another FIFO).
You can instate those FFs manually in the verilog code.

 

[d4red]

Only flop is not enough. I have to implement valid/stall, since I want to crash bubble.