As demonstrated in #9Why maximum???
The 10K should have the BOOT0 pin at 0V, then the FTDi device toggles this line high. This should then get into system memory bootloader. However the voltage is at 0.5V. The Minimum level that the BOOT0 of the STM32 (ViH) should be 0.17VDD + 0.7V which is 1.26V.>This all makes sense. My question is why when the pull down is at 10K can I still enter boot mode when the voltage going into the STM32 is 0.5V? Sometimes it fails.
0.5V is too close to the threshold for BOOT0 because it is a special port with lower thresholds.
Instead ensure it always below 0.4V for reliable logic "0". ( or even < 0.3V for more margins) The specs are in #9
I assume the FTDI is not initialized yet and thus its port is floating as an input with passive 66k nominal input and this is why it needs to execute BOOT0.
Correct me if my assumptions are wrong.
The Boot0 is at 0.5V, when toggled from 0 to 1 from the FTDi device. ViH (min) of the STM32 is 0.17VDD +0.7. This equals 1.26V. So how is this 0.5V recognised as a logic 1. I am not entirely sure if I need to add 0.7V in the equation for ViH. If not then this becomes closer to the 0.5V.>This all makes sense. My question is why when the pull down is at 10K can I still enter boot mode when the voltage going into the STM32 is 0.5V? Sometimes it fails.
0.5V is too close to the threshold for BOOT0 because it is a special port with lower thresholds.
Instead ensure it always below 0.4V for reliable logic "0". ( or even < 0.3V for more margins) The specs are in #9
I assume the FTDI is not initialized yet and thus its port is floating as an input with passive 66k nominal input and this is why it needs to execute BOOT0.
Correct me if my assumptions are wrong.
>> how is this 0.5V recognised as a logic 1.As demonstrated in #9
BOOT0 has lower thresholds than I/O ports.
Vil= 0.43 V max = 0.1 * Vdd+0.1 V <<<<< this means use 10% of the 66k pull-up for pull down = 6k6 max
Vih = 1.26 V min = 0.17 * Vdd+0.7 V
Ok, I understand. I was mis interpreting the ViH value. So the remedy is to have the pull down decreased to allow the Boot0 voltage to be less than 0.43V. Also when toggled it needs to be greater than 1.26V. The recommendation was to have it at 6.6K?>> how is this 0.5V recognised as a logic 1.
The above spec means any voltage between 0,43 and 1.26 is an invalid logic level which includes 0.5V
Invalid or indeterminate means it may be either a 0 or a 1.
I can see that a stronger pull up will keep the Boot0 pin below 0.43V. But when the FTDi is toggling, i.e. Internal pull up 66K. This does not then go above 1.26V. Forming a potential divider with the 6.6K. Am I missing something?That is the max value = 6.6k yes. for passive logic 0.
The min value is 1.26V/2mA = 0.63 k for active logic 1.
That's the question. I don't yet understand if CBUS3 pin in GPIO output mode provides active pull-up or not. It's not clearly specified in the datatsheet. If there's no active pull-up feature, you definitely have a problem with initial state before FT230x configuration is loaded from EEPROM. Default (unconfigured) state of CBUS3 is weak pull-down in USB suspend and weak pull-up when connected.Am I missing something?
I believe it's done by using FTPROG utility. Unfortunately I do not have access to code.That
That's the question. I don't yet understand if CBUS3 pin in GPIO output mode provides active pull-up or not. It's not clearly specified in the datatsheet. If there's no active pull-up feature, you definitely have a problem with initial state before FT230x configuration is loaded from EEPROM. Default (unconfigured) state of CBUS3 is weak pull-down in USB suspend and weak pull-up when connected.
Can you briefly explain which CBUS bit-bang commands your are using to control the pin?
When stating a problem do not use adjectives like stronger and higher and inaccurately defining a pull-down as pullup.I can see that a stronger pull up will keep the Boot0 pin below 0.43V. (WHAT VALUE) But when the FTDi is toggling, i.e. Internal pull up 66K. This does not then go above 1.26V. (SO WHAT IS THE VALUE) Forming a potential divider with the 6.6K. Am I missing something?
No problems, I will have another look.When stating a problem do not use adjectives like stronger and higher and inaccurately defining a pull-down as pullup.
Rather report actual values Ohms ,Volts and programmed current level of the FTDi.
This should be a simple voltage divider problem, but relies on accurate test results and driver states 0 or 1 (or off) and define all the assumptions.
The driver acts like an ideal voltage but with a series Ron that has an FTDi programmed current level for a fix voltage drop in the code. However, the minimum is 2 mA and should be sufficient unless there is something missing in your description.
Try again.
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