module I2Cagain( input CLK,
input RESET,
output SDA, //Pullup SDA and SCL in UCF
output SCL
);
reg SCLreg;
reg SDA_R;
reg [2 : 0] counter; //Divide Incoming Clock
reg [4 : 0] I2C_COUNTER; //All I2C write cases
always @ (posedge CLK)
begin
if(RESET)
begin
counter <= 0;
SCLreg <= 0;
I2C_COUNTER <=0;
SDA_R <= 1;
end
else
begin
counter <= counter + 1;
SCLreg <= counter[2];
if(counter == 7)
I2C_COUNTER <= I2C_COUNTER + 1;
case (I2C_COUNTER)
1 : SDA_R <= 1'b1; //START
2 : SDA_R <= 0; //Low Transition, START
3 : SDA_R <= 0;
4 : SDA_R <= 1;
5 : SDA_R <= 1;
6 : SDA_R <= 0;
7 : SDA_R <= 1;
8 : SDA_R <= 0;
9 : SDA_R <= 1;
10 : SDA_R <= 0;
11 : SDA_R <= 1'bz;
12 : SDA_R <= 1'b1;
13 : SDA_R <= 0;
14 : SDA_R <= 1;
15 : SDA_R <= 0;
16 : SDA_R <= 1;
17 : SDA_R <= 0;
18 : SDA_R <= 1;
19 : SDA_R <= 0;
20 : SDA_R <= 1'bz;
21 : SDA_R <= 0;
22 : SDA_R <= 1;
23 : SDA_R <= 1;
24 : SDA_R <= 0;
25 : SDA_R <= 1;
26 : SDA_R <= 0;
27 : SDA_R <= 1;
28 : SDA_R <= 1;
29 : SDA_R <= 1'bz;
30 : SDA_R <= 0; ///STOP
31 : SDA_R <= 1; ///0 to 1 or 1'bz, STOP
endcase
end
end
assign SCL = (I2C_COUNTER)> 2 && (I2C_COUNTER)< 31 ? SCLreg : 1'b1; //Internal pull up, clock need not be driven to 1?.
assign SDA = SDA_R;
endmodule