1pS = 1THz and there are no active gain devices that have
that bandwidth, let alone the excess gain*BW that a logic
would need.
Synchronous counters also impose rollover logic that drops
the attainable fClk(max) below what a simple self-toggle
stage could manage. I think you will need to look at a
hybrid counter with a couple of bone-simple, run-hot
ripple counter stages prescaling the input signal to what
sync stages can handle. Those outputs might have to be
re-registered in the end to align with the sync counter's.
Go find the hottest InP foundry flow you can, make a
CML / SCL gate library and see what a ripple and a 4-
stage sync counter can handle. I expect you will not
achieve 1THz, likely not 100GHz (although this seems
to be on the edge of achievable, looking at some
photonic high-bit-rate systems' purported data throw,
though maybe a bit too reliant on parallel lanes and
multilevel signaling).