Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Pico Processor decoder Unit

Status
Not open for further replies.

Shankar Mishra

Newbie level 1
Newbie level 1
Joined
Jun 5, 2014
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Visit site
Activity points
15
Hello All

I am facing following errors while compilation.I have tried to remove these errors but failed many times.please help me out.Thanks in advance.

ERROR:HDLParsers:850 - "E:/pico_processor/InstructionDecode.vhd" Line 97. Formal port R1_OUT does not exist in Component 'InstructionDecoder'.
ERROR:HDLParsers:850 - "E:/pico_processor/InstructionDecode.vhd" Line 98. Formal port R2_OUT does not exist in Component 'InstructionDecoder'.
ERROR:HDLParsers:851 - "E:/pico_processor/InstructionDecode.vhd" Line 108. Formal in_Funct of Controller with no default value must be associated with an actual value.
ERROR:HDLParsers:837 - "E:/pico_processor/InstructionDecode.vhd" Line 129. Width mismatch. Expected width 5, Actual width is 3 for dimension 1 of R1.
ERROR:HDLParsers:837 - "E:/pico_processor/InstructionDecode.vhd" Line 130. Width mismatch. Expected width 5, Actual width is 3 for dimension 1 of R2.
ERROR:HDLParsers:837 - "E:/pico_processor/InstructionDecode.vhd" Line 131. Width mismatch. Expected width 5, Actual width is 3 for dimension 1 of in_WriteReg.
 

Attachments

  • pico_processor.zip
    5 KB · Views: 34

This is one of the reasons I don't like VHDL...(I'll admit if your tools support 2008 then you can get rid of the component declarations)


Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
component InstructionDecoder
    port (
      in_Instruction : in  std_logic_vector(7 downto 0);
      out_Opcode     : out std_logic_vector(5 downto 0);
      out_RS         : out std_logic_vector(4 downto 0);
      out_RT         : out std_logic_vector(4 downto 0);
      out_RD         : out std_logic_vector(4 downto 0);
      out_Shamt      : out std_logic_vector(4 downto 0);
      out_Funct      : out std_logic_vector(5 downto 0);
      out_IAddress   : out std_logic_vector(15 downto 0);
      out_JAddress   : out std_logic_vector(25 downto 0)
      );
  end component;



Your component declaration in the ComponentsPkg.vhd file doesn't match the actual ports on the InstructionDecoder.vhd file. I'd wager there are probably other problems in that file, but I'm not spending the time to verify.

Regards

- - - Updated - - -

Just as I suspected all of the problems look like they are due to the package file.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top