PIC18F2550, C18 - What setting to choose for CPUDIV?

Try replacing all of your "#pragma config ..." directives with mine.
If it works, try changing my directives with yours one by one. This way, can find the directive which is causing the problem.

thank you
this information helped me a lot while configuring my 18f4550

I spent a lot of time trying to figure out how #pragma OSCX_PLLY worked. Maybe its obvious to other people, but since I had a hard time with it, maybe other people do to. The PIC18F2455/2550/4455/4550 Data Sheet mentions the following on page 293 (in the 2009 version):

CPUDIV1:CPUDIV0: System Clock Postscaler Selection bits
For XT, HS, EC and ECIO Oscillator modes:
11 = Primary oscillator divided by 4 to derive system clock
10 = Primary oscillator divided by 3 to derive system clock
01 = Primary oscillator divided by 2 to derive system clock
00 = Primary oscillator used directly for system clock (no postscaler)
For XTPLL, HSPLL, ECPLL and ECPIO Oscillator modes:
11 = 96 MHz PLL divided by 6 to derive system clock
10 = 96 MHz PLL divided by 4 to derive system clock
01 = 96 MHz PLL divided by 3 to derive system clock
00 = 96 MHz PLL divided by 2 to derive system clock

Click to expand...

I wasn't sure how those binary values (00,01,10,11) mapped onto the available pragmas (OSC1_PLL2,OSC2_PLL3,OSC3_PLL4,OSC4_PLL6) and why you couldn't mix-and-match to get things like OSC1_PLL4.

I eventually realized that the mapping was
00 = OSC1_PLL2
01 = OSC2_PLL3
10 = OSC3_PLL4
11 = OSC4_PLL6
and that the oscillator mode determined which divisor was relevant. So if you're using a mode that uses the PLL, the divisor is Y if you're using OSCX_PLLY then the divisor is Y; otherwise it's X.

Thank you kevint.

I'm running into the same difficulty in understanding the setting of CPUDIV, etc. - I'm using a XTAL of 24MHz. Following your posts, I've struggled to figure out the magic numbers. Your message has helped me a lot.

my settings could be (not tested yet)

#pragma config PLLDIV = 6 // (24 MHz crystal)
#pragma config FOSC = HSPLL_HS
#pragma config CPUDIV = OSC2_PLL3 // this one doesn't care indeed
#pragma config USBDIV = 2 // Clock source from 96MHz PLL/2

Thank you again - you are so smart a guy! :grin:

Max