PIC Interrupts caused by TMR0 overflow

[neoaspilet11]

Hello Everybody,

Please consider this case:

1.) Suppose program control is currently servicing an Interrupt caused by TMR0 Overflow, GIE bit is CLEARed.

2.) During TMR0 Overflow Interrupt servicing, an External Interrupt on RB0 occured, that is a rising edge took place and RB0 now is HIGH - this will cause the INTCON, INTF bit to HIGH.

3.) The TMR0 Overflow Interrupt service is finished, TMR0IF is CLEARed and GIE is SET again.


After program control exits the Interrupt service routine, will the external interrupt be serviced? Take note that the rising edge at RB0 already occured and INTF is HIGH already after retfie of TMR0 overflow interrupt service.

Thanks for any ideas.

 

[gidimiz]

Re: PIC Interrupts

Hi,

From the PIC16F877A data sheet, page 153:

global interrupt enable bit, GIE (INTCON<7>),
enables (if set) all unmasked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately.

Reading again yor question, i dont know why you are disabling GIE. If you are already in the interrupt, RB0 will not be serviced until the interrupt will finish.
Post what you want to do and why, and maybe I will be able to give you another way to solve your problem.

Good luck.

 

[rfmw]

Re: PIC Interrupts

I think that as soon as the GIE is set again, you'll get into the interrupt service routine again...

 

[neoaspilet11]

PIC Interrupts

Thanks for the ideas guys,

My application will use two interrupt sources, one from the External - a rising edge at RB0 and TMR0 overflow. The TMR0 is not pre scaled so it will increment on every instruction cycle and the PIC877A I used is running at 20 MHz. So therefore it is very likely that any interrupt was caused by the TMR0 overflow and the external interrupt has little chance to be triggred.

I purposely Cleared GIE at teh beginning of the Interrupt wether caused by TMR0 overflow or External Interrupt to simflipy program flow and coding.


I figured out the solution last night. And that is when an interrupt occurs either from TMR0 overflow or External Trigger on RB0, I must poll first INTCON, INTF to see is INFT is HIGH. It if it is not then service the TMR0 overflow.


Then I noticed that when an external trigger happened during TMR0 Overflow servicing, INTCON, INTF flag will be HIGH. Thus when after servicing TMR0 overflow, even if the MPU does not service RB0 interrupt, at the next TMR0 overflow, the Interrupt service routine will be forced to execute RB0 interrupt service because INTCON, INTF is HIGH thus bypassing TMR0 Interrupt service!

Again, thank you for the ideas
Jack