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With those values it is probably errors or the effects of parasitics in the component simulations and the time constant caused by R1.
Try with MUCH larger inductance and MUCH smaller capacitance.
Consider also that capacitors with those kinds of values usually have tolerances of as much as +/- 50%.
not a realistic filter.
what is your input and output impedance requirements. You are driving it with a voltage source, instead of a signal generator with a source impedance. also how are you analyzing it with a load? is the load infinite impedance? 50 ohms?
Usually when i see a ripple like that it is an impedance match issue, and the values have to be slightly adjusted. But in your case, i wonder if you are simply not analyzing it correcty
I also simed with first cap = 0 because your .1 ohm input R essentially negates the existentance
of the input cap, eg you are essentially driving input with a V source in || with input cap, so
input cap effectively not there. So circuit essentially looks like a classic LC LPF, with Q peaking
due to real losses close to zero.
If you are trying to design a PDN for a HF servo control, this is not how to do it.
LTSpice does not display actual DCR, ESR, SRF values of parts shown in schematic.
All parts have RLC values, or SRF, f , Q with DCR + L, or ESR + C, R values and if one spans more than a few decades beyond the 1st order or 2nd order effects, there will be 3rd and higher order effects in passive components unless damped by load or with active feedback compensation.
Start with assumptions on load and source impedance from load regulation error like Rs= 1% of V/I max. This creates low DC error but may create high Q resonances that must be beyond the BW of any disturbance. (impulse, step, RF)
Then make a design spec for passband (f) & tolerance [%] with ripple spec [dB max], and stopband, f [dB min] before you choose a design.
Please read up on PDN design to answer all the basic questions. ( several good books )
My Falstad web sim agrees with Simplis. +20 dB @ 500 Hz
A CLC filter with flat frequency response (Butterworth characteristic) for 100 mOhm source impedance looks e.g. like this
For given source impedance and cut-off frequency, there's exactly one set of L and C values that implements the given filter prototype.
As mentioned by KlausST, this isn't a completely defined filter application, because actual load impedance is probably not infinity as assumed in my design.
The magnitude curve shown in post #1 can be only achieved with C and L series R (about 40m respectively 500 m), and it's obviously the voltage across C1, not filter output voltage. Maximal confusion in a seemingly simple question.
Hello FVM,when i design an opamp circuit at 5MHz for example .
i have an idial source and load.
the signal generator connected to my PCB it doesnt have 100 ohms resistance. its a huge voltage drop.
there is a difference between caracteristic impedance and series resistance.
where did i go wrong with this logic?
Thanks.
If you see a huge drop thats because you are terminating your sig gen with a huge cap,
which may not have output current capability to drive filter input cap even if sig gen was
50 ohm output would look like
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