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seeravi

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Hi,
1)I want to clear DRC/LVS violations in Physical Design , which tool is sign-off ?
 

seeravi

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i am using encounter tool, what is the input to assura tool ?and also how to create rulefile
 

itsmeteja

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you can use calibre or hercules..

I/p's are gds or oasis database and spice netlist

you can get rule deck from tsmc/umc foundary..
 

rca

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verilog transform in spice netlist to be compare with gds.
 

littlechip

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import the netlist which is from PR tool into the virtuoso to generate the schmatic of the design and then export the cdl netlist from the schmatic, it works better than use V2LVS, and you can avoid some problem
 

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