Physical Limitations of Gate Size

[lordsathish]

Hi Ppl,
How does scaling down the gate size of the MOS cause power dissipation and data synchronization problems ?

Thanks

 

[jimjim2k]

Hi

This is more beyond a simple question. It is a two-folded research item.

1. Power dissipation caused by mos scaling
2. Data or clock synchronization

1.
Power = Dynamic + Static + Short Circuit
Dynamic power ~ VDD^2
VDD is reduced with scaling
Load equivalent capacitance related to MOS internal capacitances in turn technology and scale factor

2. Scaling affects clock frequency
Power ~ Clock frequency
Data synchronization ~ scaling

tnx

 

[AdvaRes]

Hi Ppl,
How does scaling down the gate size of the MOS cause power dissipation and data synchronization problems ?

Thanks

Hi,
Schrinking in feature size results in a very compact circuits. This means, particularly, that the oxyde of the transistors/capa/res of this IC becomes more thin leading to a lot of leakage. Leakage is the main cause of power dissipation in 65nm tech circuit and below.

Synchronization problem is due to interconnects. With scaling, the resistance/capacitance of the on chip wire increase. The electrical signal become more slow since delay is propotional to wire's resistance/capacitace. If this signal is a clock signal, designer will notice skews during simulation.