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Schrinking in feature size results in a very compact circuits. This means, particularly, that the oxyde of the transistors/capa/res of this IC becomes more thin leading to a lot of leakage. Leakage is the main cause of power dissipation in 65nm tech circuit and below.
Synchronization problem is due to interconnects. With scaling, the resistance/capacitance of the on chip wire increase. The electrical signal become more slow since delay is propotional to wire's resistance/capacitace. If this signal is a clock signal, designer will notice skews during simulation.