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pHEMT gate control with filtered PWM not working as expected

Hawaslsh

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Hello all,
1603212669667.png

I am working with a pHEMT amplifier, HMC7357. To control the amp I need to supply gate voltages of -1.4 and -0.8V. Ultimately I want the gate to be driven by a microcontroller's PWM output. To do so, I am experimenting with the multiple feedback amp (MFA) pictured above. The load resistor, R5, represents the gate resistance given in the amp's datasheet. To test the functionality of the MFA I first measured the drain current (Id) through the amplifier using a bench top power supply to power the gates. I then compared those results to the drain current, Id, using the filtered PWM from above.
Vgate (V)Drain Current w/ Benchtop Power supply on gate (mA)Drain current with filtered PWM on gate (mA)
-1.422
-1.11269330
-0.828491103
Despite measuring the same gate voltage (using both an oscilloscope and DC voltmeter) the same FET, under the same drain bias (6V), drew different amounts of current depends on whether the gate was driven by the benchtop power supply or my filtered pwm output.
I checked the noise remaining on the filtered PWM output, there is still ~10mVp-p on the oscilloscope. However, a 10mV offset to the benchtop power supply isn't sufficient to make the current equal.
Initial Vgate (V)Adjusted Benchtop supply Vgate to match IdId (mA)
-1.11-1.06330
-0.82-0.721040
The chart above shows how much I had to adjust the bench top supply's Vgate in order to make drain currents match the PWM case. To me, its very confusing i can measure the same DC voltage across the amp (using a benchtop supply vs filtered pwm output), but measure very different drain currents. Anyone have any thoughts as to why this might be happening?

added notes: PWM is 450Hz, 5V peak, 20mA max supply. All measurements done with NO RF input.

Happy to provide more context,
Thanks in advance!
 

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danadakk

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Is your scope averaging samples per chance ?

When you look at ripple do you set scope on infinite persistence so you can see pk-pk
ripple clearly ?

The supply vs PWM for gate drive has significantly different Z's the Igate must travel
thru. This does not matter of course if your scope is doing accurate measurements.

Schematic of PWM filter ?

Return path for PWM is "stiff", no ground loss.....? Your measurement probe points
consistent ?

Regards, Dana.
 

FvM

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The schematic is confusing because there's no 1.5k load on the gate bias input. In case you are using the evaluation PCB, there's instead a 4.7 uF bypass capacitor which may well cause problems, because OPs are generally not stable with larger capacitive loads. An series isolation resistor, e.g. 100 ohm, between OP output and Vggx pin is required.

1603270278613.png
 

vfone

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I think that if you change the value of R5 to a lower value, (let's say 100 ohms) everything will work just fine. Try it.
 

Hawaslsh

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When you look at ripple do you set scope on infinite persistence so you can see pk-pk
ripple clearly ?
Thanks for the advice. When I turn on persistence I can see +-100mV spikes every time the PWM signal switches! Those spikes are large enough, they might account for the added current.

Currently the setup is terrible! It's an arduino board suppling the PWM to a breadboard. The breadboard has through hole components to create the filter. The amp is on its own board and the filtered signal is fed from the breadboard to it (via wires of course). Do you think its the simple fact its on a bread board? As a test, I tried a third order filter and that too produced about +-100 mV noise peaks.

To FVM's point, there is no 1.5K load, its all capacitive. Sometimes the simplest things are the hardest. Adding the 100 ohm resistor loaded the op-amp's output. I tried R5 as 1K, it had little to no effect on the noise.

Thanks for the help
 

danadakk

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Thanks for the advice. When I turn on persistence I can see +-100mV spikes every time the PWM signal switches! Those spikes are large enough, they might account for the added current.

Currently the setup is terrible! It's an arduino board suppling the PWM to a breadboard. The breadboard has through hole components to create the filter. The amp is on its own board and the filtered signal is fed from the breadboard to it (via wires of course). Do you think its the simple fact its on a bread board? As a test, I tried a third order filter and that too produced about +-100 mV noise peaks.

To FVM's point, there is no 1.5K load, its all capacitive. Sometimes the simplest things are the hardest. Adding the 100 ohm resistor loaded the op-amp's output. I tried R5 as 1K, it had little to no effect on the noise.

Thanks for the help
You are going to have to look at your ground situation as a thought. Common ground, as close
to source as possible.

Cap technology matters, not all are equal in bypass (ESR) performance for the same C -

1603314183497.png

Basic message poly tants best for bulk, MLCC for HF ceramic work. Together they are best.

Probing, a good ap note on it - https://www.tek.com/document/primer/abcs-probes-primer


Regards, Dana.
 

dick_freebird

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I don't think this is very desirable (PWM drive
of a MMIC gate bias pin).

From working on element controllers that
included gate control (active bias) I know
that the microwave guys say it's key to have
a very low-impedance and very quiet gate
bias. I don't consider a buck converter, to
be that. Adding filtering may knock down
HF synchronous noise but adds resistance
and that makes random LF noise, which
will transform to close-in phase noise.

Gate bias should be low current. What's so
wrong about a LDO? Or an op amp that can
buffer a better-filtered PWM image to low Z,?
 

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