Phase Shift Full Bridge SMPS is massively over-hyped?

[treez]

the simulation in the top post shows that the normal leakage inductance in the full bridge transformer prevents the reverse recovery current (of the secondary diodes) from flowing in the full bridge FETs...

...I am quoting myself here, this is the full quote, and I stand by it. Running the simulation in the top post emphases it. The simulator is far from perfect but it gets this right.
We’re all talking of switch-on RFI in the full bridge as if it’s a showstopper for the full bridge. What about the hard turn-off losses that we get with the PSFB?

Yes a booster does it, but the diodes are well chosen and they do dissipate a lot of heat at 3kW due to reverse recovery, wind up the turn on on the boost fet and the diode will die unless it is incredibly well heat-sunk, building one would show you this

…Thanks, but we have a 3kw EV charger purchased. We took it apart, it contains two boost PFC stages which run alternately (one on for 10ms, then off, then the other one on for 10ms, etc etc), and it also contains a half bridge LLC resonant converter following the boosters.

The two boost FETs and diodes don’t have any more heatsinking than the LLC FETs/diodes. They are all just clipped to the sides of the metal enclosure. When you touch round the enclosure, the hottest bit is at the 4 LLC converter output diodes. The part near the LLC fets is similar temperature to the part near the boost PFC FETs and diodes.
The boost PFC uses infineon FETs and diodes.

 

[Easy peasy]

PSFB has caps across the mosfets (typ 1nF 1kV), these limit dv/dv at turn off and allow the fet to be properly off before the volts rise too much, you can achieve this in a std FB too but the dv/dt is higher...much higher...

If you try and turn on a fet fast in a std FB in order to try and have it fully on before the current rises too much, the dv/dt is high, and, as it is connected to the Tx winding ends, this high dv/dt propagates thru the whole unit causing RFI interference issues, the high dv/dt is seen across the o/p diodes, leading to increased di/dt, leading to increased diode losses at turn off...
Un-usually high leakage is not that helpful as it requires extra snubbing when the diodes turn off.
This is the difference between simulation and real world converters....

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we have a 3kw EV charger purchased

, how long will it run at full power? a lot of chargers are designed based on the fact that they do not have to deliver full power for very long as the battery voltage comes up and the required current goes down...
Each booster is 1.5kW average, why did they not do a 3kW booster? the answer is in the above posts....

 

[treez]

PSFB has caps across the mosfets (typ 1nF 1kV), these limit dv/dv at turn off and allow the fet to be properly off before the volts rise too much

Sorry the ltspice simulator shows that putting caps across the PSFB FETs as you describe increases losses in the FETs
The attached simulation shows the PSFB converter with and without caps as you describe.
I appreciate this is the simulator, but simulators can do this kind of stuff and prove/disprove a point.

 

[Easy peasy]

How is it then that all real world PSFB converters at 3kW and above have caps across the fets....?

 

[Velkarn]

Treez, you did not put inductance in series with primary. it needs to be for proper PSFB working.

 

[treez]

Treez, you did not put inductance in series with primary. it needs to be for proper PSFB working.

thanks, there is inductance in series with the primary, the coupling factor of the transformer is 0.97, so the leakage inductance performs this function.
There is a leakage term, as seen from the primary, of 88.7uH, due to the 0.97 transformer coupling. {(1-k^2)*1.5mH}

How is it then that all real world PSFB converters at 3kW and above have caps across the fets....?

This is interesting , there's no way I would implement caps across the fets in a PSFB unless it was shown to give benefit on the simulator first.
As is known, its a pretty golden rule of the ltspice simulator with general smps type stuff like this. If the simulation works, it means nothing, but if the simulation doesn't work, or shows poor operation, its virtually guaranteed that the real circuit, if built , won't work well either.

 

[Easy peasy]

unfortunately all computer simulations suffer from the GIGO effect...

 

[FvM]

To take advantage of parallel capacitors, the phase shifted bridge must implement ZVS operation. Obviously that's not the case with your simulation setup.

 

[Velkarn]

thanks, there is inductance in series with the primary, the coupling factor of the transformer is 0.97, so the leakage inductance performs this function.

i don`t recommend use of coupling factor to simulate leakage inductance in LTspice. there is an experience when in this case the work (in simulator) of power converter was abnormal. i think its because in transformer`s model coupling factor "produces" some kind of "virtual" leakage inductance. in PSFB in this inductance energy store, so where energy will be stored with coupling factor?

besides, FSFB needs very precise tuning of parallel caps and series inductance. to archive zvs it needs to be well tuned. it is not so "draw in simulator and ok"

 

[FvM]

i don`t recommend use of coupling factor to simulate leakage inductance in LTspice. there is an experience when in this case the work (in simulator) of power converter was abnormal. i think its because in transformer`s model coupling factor "produces" some kind of "virtual" leakage inductance. in PSFB in this inductance energy store, so where energy will be stored with coupling factor?

Sounds confused. The SPICE coupled inductance model can be well mapped to other descriptions, e.g. the classical Lp and Ls transformer equivalent circuit. Of course limited to linear transformer operation. Otherwise saturated core models must be used.

When you consider that a coupling factor less than unity establishes a leakage inductance, so yes it can "store energy". In any case, the energy is stored in the magnetic field, specifically in the air gap respectively the stray flux linked to leakage inductance, whatever abstraction level is used in your model.

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As a principle limitation, the coupled inductance description can only mode bilateral mutual couplings. So if your transformer has more than two ports with individual leakage parameters, you have to proceed to a different description, either multiple coupled inductors or controlled sources as a more general model.

 

[mtwieg]

I find that LTspice's transformer model to be valid so long as you're fine with a completely linear approximation. Given two inductances and a coupling coefficient, there are a few ways to represent the equivalent circuit, with the leakage inductance either distributed between the two windings or lumped onto one winding. Some time ago I struggled a lot with whether such a representation was adequate, but ultimately I found that it is because all of those equivalent circuits behave exactly the same from a black box perspective.

However for a PSFB design I would personally draw the leakage inductance as a separate component while keeping the transformer K constant, since this is how it's usually implemented in real life, and because it gives more insight into the role of the leakage inductance since you can probe its voltage.

 

[treez]

The following LTspice simulation certainly shows zero voltage turn on (in both active and passive legs) of PSFB converters with and without capacitors across the power FETs. However, no benefit in the FET losses is shown by having the capacitors across the FETs in the PSFB, other than the reduced dv/dt. As you have said, the lesser dv/dt of the FETs at turn off, should reduce the reverse recovery losses in the secondary diodes of the PSFB.

There is still significant overlap of voltage and current at switch off of the power FETs in the PSFB that have the capacitors across them.

The added capacitances across the FETs will also mean that the series “Leakage” inductor will need increasing in value in order to give zero voltage turn on at lighter loads. This increased value of leakage will mean duty cycle loss, -as has been said, this can in part be addressed by adjusting the turns ratio, though in the 360Vout example shown, this would mean the secondary diodes suffering even more voltage stress.

None of the design examples, or PSFB literature on the web show capacitors being used across the PSFB FETs. Also, none of the literature anywhere speaks of achieving zero, or even low voltage turn off of the FETs of a PSFB converter.

As before, its worth noting that the natural leakage inductance in the Full Bridge converter transformer is doing a good job of giving zero voltage turn on of the FETs, despite this not being a “resonant” topology.
The full bridge transformer’s leakage inductance also staunches the reverse recovery of the secondary diodes. I cannot see the conditions for bad reverse recovery in the full bridge, due to the leakage inductance effect of mitigating it. (admittedly I used non Reverse recovery Schottkys in the simulation, as don’t have UF type).
The simulation shows the secondary diodes of the full bridge converter have stopped conducting before the reverse voltage builds up across them. As you know, this is due to the leakage inductance in the transformer.

 

[Easy peasy]

Dear Treez, if you ever get around to building a high power PSFB (or a hard switched version) I think it highly likely you will look back on many of the above comments and wish you could erase them.... speaking as someone who has solved all the practical issues in 1 - 14kW converter design...

 

[treez]

We are now building a 7kW SMPS, for charging batteries. Vin = 400VDC, vout = 300-410VDC. We chose the LLC converter , as we couldn't find diodes with low enough trr (and enough voltage rating) for the phase shift full bridge.
Here is simulation of the LLC..(in LTspice).

 

[Easy peasy]

Good luck with your build, we have had good success with phase shift control of series resonant converter also at this power level, esp no load power, 500-800Vin, 350VDC out (40A)

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remember in power electronics, all components are rated in Amps rms, including the resonant caps and o/p filter caps...

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and the caps across the H bridge...

 

[treez]

This was in relation to the situation of increasing leakage inductance in a full bridge...

Un-usually high leakage is not that helpful as it requires extra snubbing when the diodes turn off.

Thanks, though I don't believe that a greater leakage inductance, within reason, does actually mean more loss in the secondary diode snubbers of a full bridge...the attached simulation of full bridge's with differing leakage bears this out. (sim called "Full Bridge Snubbers")

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this is largely because you cannot turn the fets on really fast and hard in a std H bridge as you will hit the o/p diodes really hard in doing so, upping losses and RFI

In the attached LTspice simulation of a full bridge SMPS, (sim called "full bridge reverse recovery") with only small leakage inductance, there is no (or just very minimal) reverse recovery loss seen in the output diodes, despite the full bridge fets being turned on quickly. The minimal lekage inductance, in a well coupled full bridge transformer, is enough to prevent reverse recovery of the full bridge output diodes, from becoming a significant problem.

(On a different note, apologies to linear.com for my moaning that there are no HV UF didoes in their simulator...just downloaded the latest version and its packed full of them.)

 

[Easy peasy]

It is turning the fets on V-fast, not off, that causes the diode reverse recovery problems...

 

[treez]

Thankyou , my mistake (now corrected above), I meant to say turning on. The corrected version above still applies...reverse recovery is not significantly seen in the full bridge as in post above (#36)

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Another problem with the PSFB, is that the dead time of the FETs needs to be set correctly such that zero voltage switching (at turn on) occurs. ZVS at the turn on transient is especially important for a PSFB converter, because of the capacitors across the fets (1nF caps). If the PSFB does not ZVS at turn on, then the sudden discharge of the parallel capacitors (across the FETS), will cause extra switching losses at turn on, as well as extra EMI problems..

..Now suppose that the FETs in a PSFB design go obselete. This means that a fully fledged PSFB design engineer (as we all know there aren’t many of these around) needs to be on hand, ready to select replacement FETs. The unit then needs re-testing with these new FETs over the load range. This is a serious downside of the PSFB. It means it never really gets out of the engineering design department.
(of course, it’s not necessarily bad for a PSFB design consultancy, who can profit from the extra work)

If the PSFB was way more efficient than a Plain Full Bridge converter, then fine , maybe its worth the extra effort. But I think that these threads have shown that the PSFB is not “really significantly” more efficient than a full bridge converter. (speaking of <430VDC input cases)

The PSFB , for a start, has a lot more circulating primary current than a Full Bridge, causing extra I^2.R losses there.
The PSFB has ZVS at turn-on, but turn on switching losses in a Full Bridge are not significant enough to really let the PSFB shine out here. Also, the Full Bridge does not suffer significant enough reverse recovery losses in the secondary diodes to make the PSFB shine out there either.

The nice thing about the PSFB is that the ZVS (at turn on) can be arranged over a wide load range, (due to the PSFB’s circulating current and by increasing the leakage inductor in the PSFB) and this then means that one can also reduce the turn off switching losses of the PSFB by having caps across the FETs. (because the ZVS at turn on means that there is no dissipative discharge of the “caps across the FETs” at turn on.)

However, having caps across the FETs in the PSFB does mean that when extremely lightly loaded, there will be more losses than in a standard full bridge converter on extremely light load.

Also, having a larger leakage inductor in a PSFB (which is needed when you have caps across the FETs), also means more 'duty cycle loss', and then one has to increase the turns ratio of the transformer, and with higher voltage outputs, that then means more voltage stress on the output diodes.

I believe in summary from these threads kindly donated, that the PSFB is more efficient than the Full Bridge (excluding extremely light load). Also that the PSFB can be done with lower EMI than the full bridge. However, the improvement is not significant “enough”. –In other words, not enough to make it worthwhile putting a converter out into the field that is going to need a design engineer on hand to sort out what happens if the FETs go obselete. There just aren't enough PSFB-capable design engineers in the world.

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Regarding adding capacitors across the FETs in a PSFB..this comes with disadvantages too…

Page 9 of the following actually advises us to reduce the capacitance across the FETs in a PSFB, for good reasons…

Design note DN2013-01 (by infineon.com)
“Design of phase shifted full bridge converter with current doubler rectifier”
https://www.digikey.com/web export/.../mkt/coolMOS/ZVS_Full-Bridge.pdf?redirected=1

Here is the quote….
“If we consider both energy and time ZVS design equations discussed above, we can see that increasing the leakage inductance can increase the energy available for ZVS, thus extending the ZVS load range, but on the other hand it has a side effect of decreasing the resonant frequency during voltage transition, thus increased deadtime is required, which is not desired in high switching frequency applications. For that reason, it is logical to reduce the capacitive energy in the circuit rather than increasing the inductive energy, this implies the necessity of low MOSFET’s output capacitcance for this converter and for other ZVS topologies in general.”

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More woes for the PSFB are seen on page 12 of the above document…This concerns the fact that during highly transient conditions, there is a risk of destruction of the PSFB FETs, if they are not chosen properly. Once again, the subject of FET obselesence therefore comes up with the PSFB…this isn't such an issue with the plain full bridge converter


“Robust body diode with fast reverse recovery. Although that in normal operation the body diode current/charge are softly commuted, in some conditions such as startup, load transient, light load or low leakage inductance, body diode may have hard commutation, it may not have a channel conduction following its own conduction, or channel conduction might be too short and not enough to completely sweep out the reverse recovery charge, in such case, as the MOSFET turns off with a high dv/dt while there are still residual charge in the body diode region, the charge leaving the body diode P-region may bias the parasitic npn BJT, causing false turn on and destruction of the MOSFET.”

The chances of the FET body diode being very hard reverse recovered is not an issue in the Full bridge converter, -it is however an issue, in the PSFB, as the infineon app note discusses

 

[Easy peasy]

it's lovely to see such insightful engineering observations based on absolutely no practical experimentation of the std full bridge versus the FSFB, there are so many other engineering effects that govern the choice of topology at high power...

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if you do build one, you may discover why nobody uses built in leakage inductance of a transformer as the extra L...

 

[treez]

thanks, do you mean like a sectioned bobbin?...we don't wish to do that, not for the PSFB or FB. If we needed in in PSFB , we would add an extra inductor for that purpose. As you know, in an isolated offline transformer, even with interleave winding, there will always be some leakage inductance.