Phase shift full bridge controller datasheet gives misleading info?

Status
Not open for further replies.
T

treez

Guest
Page 1 of the UCC28951 datasheet states………………..


UCC28951 datasheet:
https://www.ti.com/lit/ds/symlink/ucc28951.pdf

..However, this is misleading, it is not adaptive delays that help to bring about ZVS….rather, it is the sizing of the primary side series inductor…this is confirmed by the following document…
Simplified Phase-Shifted Full-Bridge Converter Design

**broken link removed**
…..where it says…

Would you agree that the UCC28951 datasheet is misleading here?
 

Adaptive delays help you balance ZVS operation with dead time diode conduction losses.

On a super quick look they tie the ADEL (adaptive delay) pin to the current sense so dead time can change with current. That makes sense since low currents mean slower commutation and mean you need more dead time for ZVS operation. But you don't want long dead times all the time because it means diode conduction losses at higher currents.


I've seen chips with an alternative scheme of sensing the switch node voltage and 'seeing' when it has commutated.
 
Reactions: treez

    T

    Points: 2
    Helpful Answer Positive Rating
the dead time of the so called passive leg of the H bridge needs extending at light load as there is insufficient energy/current for the voltage to completely swing to the other rail in a short time - so a longer time is needed for it to get close to the other - hence adaptive dead time.

We have used additional commutation chokes in our larger converters to ensure the passive ( or lagging leg ) side always has plenty of current at turn off - so the dead time can be fixed and ZVS is achieved over the full load range

I have not considered the effects w.r.t sec side fet operation ...
 
Reactions: treez

    T

    Points: 2
    Helpful Answer Positive Rating
Additional parallel or series inductance? Only parallel inductance could ensure ZVS at very light or no load (while adding circulating current losses).

Gan or SiC is helpful to deal the light load hard switching in this topology and widen the range of ZVS operation due to lower C.



I answered hastily above before seeing your post already cited diode losses: Simply put if you don't have adaptive control you'll probably choose a dead time that's lower than if you do, clamping off some possible ZVS operation.
 

Additional parallel or series inductance?
Click to expand...
neither, from the mid point of the leading leg to a fixed V point.

I think the term leading leg refers to the leg that turns on to initiate a power pulse thru the Tx, this is the one starved of current at light load - the lagging leg is the one to turn off at the end of a power pulse and therefore always has some current ( except at close to zero phase shift ) ...
 
Reactions: treez

    T

    Points: 2
    Helpful Answer Positive Rating
Another point of contention in the UCC28950 datasheet is on page 61...

Page 61 of the UCC28950 PSFB (with sync rects) controller datasheet states that an RCD clamp is needed across the sync rect FETs to “avoid overvoltage due to switch node ringing”.
…But surely the RCD clamp in such a case is there to stop overvoltages which come about due to brief reversals of the secondary inductor current when the sync FET turns OFF whilst flowing reversing inductor current….the RCD clamp prevents overvoltages from that incidence.
Surely the switch node overvoltage ringing would be there even if the sync fet was not there (ie just a diode there)…and this ringing would be addressed with RC snubbering, not an RCD clamp?

UCC28950 Datasheet
https://www.ti.com/lit/ds/symlink/ucc28950.pdf
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…