Phase Margin in PLL [hlp]

[No one]

Hello Everyone;
What is the phase margin in the loop filter of PLL? Please explain.

 

[biff44]

If you are going to work with PLLs, you really need to study classical control theory/linear systems. But basically, if you have a feedback network with a forward (complex) gain of G(s), and a feedback gain of H(s), the closed loop system gain is G(s)/(1 + GH(s)).

(s is just a fancy way of saying frequency in radians/second, and refers to the control loop frequency (DC to say 1 MHz), not the PLL microwave output frequency!.)

So, at the frequency where the maginitude of |GH| = 1, and the phase angle of GH = 180 degrees, the system gain is 1/(1-1) = 1/0 = infinity. ie unstable.

BUT, you can have a condition where |GH|=1 and phase angle GH ≠ 180, and the system can be perfectly stable.

How close to 180 degrees in phase your system is when |GH| crosses unity, in a simple system, determines if the system is stable, unstable, undershoots, overshoots and rings, etc.

I like to have 60 degrees of phase margin when I can get it.

In your basic PLL, since there are usually two integrators (the VCO itself and the loop filter), the gain is monotonically decreasing with increasing frequency, so the gain |GH(s)| crosses unity at only one frequency, called the "open loop bandwidth", so to a first order you only have to look at that one frequency point.