Paul678
Newbie level 6
From this paper:
http://www.elenota.pl/datasheet-pdf/88472/National-Semiconductor/AN-1001
"When designing for a higher phase margin you trade off
higher stability for a slower loop response time and less
attenuation of the Reference Frequency."
Is this true for ALL PLLs?
And it would seem the converse is true with the loop
bandwidth, because a wider, higher loop bandwidth
gives you a faster acquisition time (Settling time), but
may make the loop less stable, and will attenuate the
Reference spurs less.
Thoughts?
http://www.elenota.pl/datasheet-pdf/88472/National-Semiconductor/AN-1001
"When designing for a higher phase margin you trade off
higher stability for a slower loop response time and less
attenuation of the Reference Frequency."
Is this true for ALL PLLs?
And it would seem the converse is true with the loop
bandwidth, because a wider, higher loop bandwidth
gives you a faster acquisition time (Settling time), but
may make the loop less stable, and will attenuate the
Reference spurs less.
Thoughts?