I am going to design a FM modulator based on digital phase locked loop as my final year project. Mainly the FM modulator. The modulator should be programmable to generate FM carrier frequencies in 100 kHz steps. Transmission frequency range: 88MHz - 108 MHz. There should not be interferences between each channel.
Here is the basic block diagram
**broken link removed**
Here I am going to use 74HC4046A IC for the digital phase locked loop and 74HC4059 IC for the programmable divided by N counter. Since the 74HC4046A Ic not working in the FM broadcasting band, a bandpass filter will be used to filter out the desired frequency range from the produced harmonics at the VCO.
I have few questions.
- What are the benefits/advantages of using digital phase locked loop for FM modulation?
- Is it possible to use the 74HC4046A IC for the design? What things should I consider?
- How do I make the 74HC4059 IC as programmable to select the desired chaneel?
- What are the other yhings I should concentrate when I designing this?
Code C - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 /*****************************************************************************/ /* FM-PLL.c */ /* */ /* This program monitors the state of the DIP switch on the PLL PCB, sending */ /* new config data to the LMX2337 PLL IC when the switch value is changed. */ /* */ /* The output frequency = 88.1 + (DIP switch) x 0.1 MHz (to a max. of 107.9) */ /* */ /*****************************************************************************/ #include <pic.h> /* PIC details, selected by compiler options */ __CONFIG(PROTECT|FOSC1|FOSC0); /* RAM prot(for 16f/c84),RC osc, no watchdog */ #define slatch RA0 /* Latch enable control signal to PLL */ #define sdata RA1 /* Serial data to LMX2337 PLL */ #define sclk RA2 /* Serial clock to LMX2337 PLL */ void writeSynthesiserWord (unsigned long configWord) { unsigned char i=21; slatch = 0; /* Low -> LE to signify start of config data */ do { sclk = 0; sdata = (configWord >> i) & 0x1; /* Send data MSB (Bit 21) first */ sclk = 1; /* Toggle sclk to clock in data bit */ } while (i-- != 0); slatch = 1; /* Latch 22 bit word into the PLL */ } void updateSynthesiser (unsigned char controlByte) { unsigned long a, b; /* A & B correspond to the LMX2337 registers */ unsigned long totalDivisor, Fout, outputWord; Fout = 881L + controlByte; if (Fout > 1079) /* Limit output frequency to 107.9 MHz */ Fout = 1079; totalDivisor = 5L*Fout; a = totalDivisor & 0x3F; b = totalDivisor >> 6; outputWord = (b << 9) | (a << 2) | 0x1; /* Compile RF2 divisor */ writeSynthesiserWord(outputWord); } void initialiseSynthesiser (unsigned char initialValue) { /* Program RF1 */ writeSynthesiserWord(0x080002); /* Set R divisor */ writeSynthesiserWord(0x200003); /* Set A & B and disable RF1 */ /* Program RF2 */ writeSynthesiserWord(0x1607D0); /* Set R div=500, Icp=5mA, FoLD=RF2 LD */ updateSynthesiser(initialValue); /* Write initial values of A & B */ } void main (void) { unsigned char switchValue; unsigned char lastSwitchValue; RBPU = 0; /* Enable weak pull-ups for PORTB inputs */ TRISA = 0x0; /* All PORTA bits configured as outputs */ TRISB = 0xFF; /* All PORTB bits configured as inputs */ initialiseSynthesiser(PORTB); /* Set configuration registers of the PLL */ while (1) { switchValue = PORTB; /* Read binary word from the DIP switch */ if (switchValue != lastSwitchValue) { updateSynthesiser (switchValue); lastSwitchValue = switchValue; } } }
Answers:I have few questions.
1.What are the benefits/advantages of using digital phase locked loop for FM modulation?
2.Is it possible to use the 74HC4046A IC for the design? What things should I consider?
3.How do I make the 74HC4059 IC as programmable to select the desired chaneel?
4.What are the other yhings I should concentrate when I designing this?
Answers:
I think your block diagram has a problem with the 4059 as I don't think it is fast enough to be clocked at the VCO frequency of 88-108MHz. So your proposed system won't work.
SMD? :O But I found a DIP-16 package for 4046A.4. You might want to consider adding a frequency display (LCD or LED) and a small MCU chip to provide the user interface. Also, are you going to use SMD components and if so you need to consider how you will make your PCB.
If you can provide a good modern IC number which is suitable for this, it will be a great help. I searched for such ICs, but all of them are coming with SMT packaging. :-(Because the 4059 divider won't work at 88-108MHz you should consider using a modern PLL chip containing the divider, phase detector etc. This can be controlled by the same MCU chip (AVR/PIC) that drives the display and accepts inputs from up/down tune buttons.
We were assuming he knows that he will need a < 100 Hz loop bandwidth in the PLL. FM receivers do not work at low frequencies, so he can throw away the 20 Hz to 100 Hz range with some impunity.
I agree with Jim.
There should be a LPF at the output of the phase comparator otherwise three problems will occur. 1 - digital 'noise' from the comparator will feed back into the loop and 2 - the audio input will attenuate the control voltage and 3 - as pointed out by Jim, the PLL will do it's best to cancel the modulation because it will see the audio as being a deviation from correct frequency and try to correct it.
Answering the other question, just set a binary number at the input of the 74HC4059. If within achievable range, the output will be that number multiplied by the reference frequency.
Brian.
Can you briefly explain about this condition?4. The linearity of the VCO, FM broadcasts should have ~ .1% THD from mic to loudspeaker!!
Frank
Ohh.. That's a bad news for me.Whoops, I just realised you are intending to use the VCO inside the 4046 and pick out a harmonic. (I thought you were just using the phase detector section of this chip)
Using the 4046 VCO is a bad idea for lots of reasons. One reason is that each time you multiply by 2 you degrade the phase noise by 6dB.
With a 4046 you would have to multiply by 10 and this would mean a 20dB degradation. Also, you would need to heavily filter the output to suppress unwanted harmonics of the VCO.
Also, you would have to synthesise in 10kHz steps to get 100kHz steps meaning the PLL divider noise will be high. The VCO inside the 4046 will be noisy anyway so this really isn't a good approach.
If SMD is not allowed you could use something like a Motorola MC145152-2 PLL IC in DIL package with a dual modulus (div 16/17) prescaler (eg Fujitsu MB503) but these DIL parts are old and hard to obtain. You would also have to make your own VCO at 100MHz but this isn't really that difficult even if you use leaded parts rather than SMD.
I agree. A few years ago I designed a stereo modulator and did it all in a cheap MCU chip. It required some very efficient code to do everything within the alloted sample period (i.e. not many MCU clock periods are available per sample to read both ADC channels and do the modulation and add the pilot tone and then send out the modulated signal)Is this a university project? If so, the VCO-only method is pretty uninspiring, why not do something challenging like PLL or better still improve on the DDS based method like the link I described above.
Hmm.. packaging of MAX2606 is surface mounting. However let me think about that IC again. :smile:BTW Thylacine1975 points out to me that I gave you a bum Maxim part number. Try the MAX2606.
Whoops, I just realised you are intending to use the VCO inside the 4046 and pick out a harmonic. (I thought you were just using the phase detector section of this chip)
Using the 4046 VCO is a bad idea for lots of reasons. One reason is that each time you multiply by 2 you degrade the phase noise by 6dB.
With a 4046 you would have to multiply by 10 and this would mean a 20dB degradation. Also, you would need to heavily filter the output to suppress unwanted harmonics of the VCO.
Also, you would have to synthesise in 10kHz steps to get 100kHz steps meaning the PLL divider noise will be high. The VCO inside the 4046 will be noisy anyway so this really isn't a good approach.
If SMD is not allowed you could use something like a Motorola MC145152-2 PLL IC in DIL package with a dual modulus (div 16/17) prescaler (eg Fujitsu MB503) but these DIL parts are old and hard to obtain. You would also have to make your own VCO at 100MHz but this isn't really that difficult even if you use leaded parts rather than SMD.
although the frequency can only be varied by approximately ±3 MHz around the midrange frequency set by the coil L
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