This is not that uncommon. The reason is usually one of the following:
1) the PLL chip does not support the exact divisor ratio that you pick. Even though it the data sheet might tout "divides from 100 to 20,000", there are often non-allowed divisors, such as 167-178, 1902-1988,....
The manufacturer often provides programming software for the chip that runs on a PC computer. Try programming in your exact reference frequency, VCO frequency, and PD comparison frequency, and it will tell you if it is valid or not.
2) Maybe it is not really phase locked? Try moving the reference frequency, say 10 KHz, and see if the VCO frequency really jumps 10 KHz X divisor ratio.
3) Check the VCO tuning voltage at 2410 MHz. What is it? To phase lock any lower you would need to go lower in tuning voltage than that. Can you? In other words, are you locked at 0.1 Volts, and to tune any lower you would have to go negative, but you can not since the VCO varactor would forward bias, or some other limiting phenomenon. Your loop filter is purely passive, so you are going to be limited to how much tuning voltage you can generate. Maybe you need to add an op amp to get a bigger tuning voltage range (or a VCO that better falls into the frequency range you need).
4) and of course, the ever present misprogrammed bit problem. Maybe you are just sending it the wrong bits! Once again, the manufacturers PC control program is your friend. Program in your frequencies, and look at what bits the PC control program is sending to the chip. Is this the same bit pattern you expected?