Peaking in Differential Cascode TIA with Emitter Follower Stage

[uqugw]

Dear community,


I’m currently working on the design of a broadband transimpedance amplifier (TIA) for high-speed optical communication. My target specifications are a bandwidth of 70 GHz and a transimpedance gain of 60 dBΩ.

Initially, I implemented a differential cascode topology with negative resistive feedback. However, the standalone TIA stage could not meet both the gain and bandwidth requirements. To overcome this, I cascaded the TIA with a variable gain amplifier (VGA) and inserted an emitter follower (EF) as a buffer stage between the TIA and VGA.

Interestingly, I observed a peaking of nearly 10 dB in the frequency response when the emitter follower was added — even before the VGA stage. This peaking wasn't present in the standalone TIA, and I suspect it could be related to damping factor issues or resonance at the high-impedance output node of the cascode.

However, when I use a common-emitter (CE) topology with negative feedback, I do not observe such peaking, even with the same emitter follower and VGA configuration.

I would appreciate any insights on the following:

• What could be the underlying reason for this peaking in the cascode + EF configuration?
• Why does the common-emitter TIA behave more stably under similar conditions?
• Are there recommended design practices or compensation techniques to mitigate this peaking while preserving bandwidth?
• Don't Cascode topology supposed to have better bandwidth performance than CE topology (with EF and VGA stage)?

Thank you in advance for your time and suggestions!

 

[mtwieg]

• What could be the underlying reason for this peaking in the cascode + EF configuration?

My guess would be added phase shift in the open loop transfer function, either due to the added capacitance on the TIA output or due to the EF itself.

• Why does the common-emitter TIA behave more stably under similar conditions?

I'm assuming the "common-emitter TIA" means just the TIA alone with feedback from its output. Obviously this would not have the phase shift added by the EF.

• Don't Cascode topology supposed to have better bandwidth performance than CE topology (with EF and VGA stage)?

Cascode will increase input impedance by eliminating most of the miller capacitance in the TIA.

Whether this improves bandwidth depends on how you measure bandwidth. For example, if you drive the TIA input with an ideal voltage source, then the miller capacitance won't matter so much.

 

[uqugw]

Thank you for the reply.

As discussed in a previous thread,

The standalone differential cascode TIA shows no peaking. The issue observed while adding an emitter follower buffer, which introduces ~20 dB peaking at high frequencies( at 61GHz). I wanted to understand the reason behind this, and looking for a solid reason for the cause of peaking. Hence, I did an open-loop AC analysis to plot voltage gain and phase margin(ref: attached testbench and results of open-loop analysis).

I expected peaking would be due to an underdamped response (suggesting low phase margin). But I observed that open-loop analysis shows a high phase margin, contradicting the expected instability.

The gain crossover was observed at 298GHz phase at the same frequency, is -113.
phase margin = -113+180 = 67 degrees, which suggests a stable system, which contradicts the peaking situation.

I’ve explored the open-loop behaviour, and while the peaking suggests underdamping, the phase margin appears stable. I suspect the issue could stem from interaction effects at the emitter follower or incorrect loop break methodology. I’d like your thoughts on how best to model or isolate the internal poles of this cascaded structure. I have attached the testbench screenshot and observed result plot for both closed-loop and open-loop analysis.

I don't get a solid explanation for this condition. Kindly suggest your thoughts on this

Thank you in advance for time and suggestion!

 

[mtwieg]

I don't think breaking the feedback loop like that will give a correct estimate of open-loop gain or closed-loop stability.

I recall that this analysis is much trickier for inverting amps than it is for noninverting, and especially confusing for transimpedance amps. Often series/shunt models are used for this analysis, but it's been a long time since I've done it myself: https://pasta.place/scraping/ETIT/P...n/SS20/Operationsverstaerker/Stability_en.pdf

From you plots it seems the gain peaking is evident in the transimpedance, but not the voltage gain. So clearly how the "input" of the circuit is defined makes a big difference. Also the stability will depend greatly on the source impedance (as it is effectively part of the feedback loop).