PCIe (Xilinx ML605) - Problem

[Pete.Cannan]

Dear Friends

I'm working on ML605 development board to benefit from its PCIe facilities. I tried to synthesize and implement PIO application example provided by Xilinx. When I use the bitstream provided by Xilinx for PIO (xapp1022), I can detect the PCIe endpoint in Device Manager and can communicate with the board.

When I implement PIO with an appropriately generated CORE, I fail to detect the PCIe endpoint.

I need your helps and comments to resolve my problem.

TIA

Pete Cannan

 

[vlsi_whiz]

Have you checked the configuration parameters of the PCIe EP Core... when you generate the core you have to fill in certain parameters... if you do not choose the BAR address space and other parameters correctly.. the EP will not be detected..