tariq786
Advanced Member level 2
Hi
I have a question about opencores pci to wishbone bridge. In the test bench, the designers have set the pci clock period to 30ns (33 MHz) and similarly set the clock period of wishbone clock to 10ns (100 MHz) to test it.
From this it makes sense because pci bus has a frequency of 33 MHz and wishbone bus has a frequency of 100 MHz.
But isn't the bridge suppose to work for arbitrary frequency of pci and wishbone? If that is not the case, then why don't we have frequency of AHB bus and APB bus specified like pci and wishbone bus is specified?
Does my question make sense?
Please help me gain insight?
I have a question about opencores pci to wishbone bridge. In the test bench, the designers have set the pci clock period to 30ns (33 MHz) and similarly set the clock period of wishbone clock to 10ns (100 MHz) to test it.
From this it makes sense because pci bus has a frequency of 33 MHz and wishbone bus has a frequency of 100 MHz.
But isn't the bridge suppose to work for arbitrary frequency of pci and wishbone? If that is not the case, then why don't we have frequency of AHB bus and APB bus specified like pci and wishbone bus is specified?
Does my question make sense?
Please help me gain insight?
