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PCI Express Interfacing

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sebas

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Hi,

Sorry if I'm posting a little bit out of topic here but I'm kinda confused. I read about the PCIe protocol, I read the Xilinx documentation about their PCIe EP and I have a quesstion: I understand that the CPU, through the RC, controls the transfer (issuing a read or write command) but how does the processor know when to issue the read command? I mean if I have a memory, on the EP side, that is updated every lets say 3 sec with new data how do I read the new data: does the software on the CPU side have to make read requests every 3 sec or does the EP signal an interrupt every time new data is available, or...?

Thanks,
Sebastian
 

Scrts

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I don't know exactly about xilinx pcie endpoint, but I suppose there is data_ready signal?
 

sebas

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Ok, data ready signal, but that's on the EP user interface side. The RC receives only TLPs so my question was if there's a specific TLP that signals that to him, is it DTLP that doesn't concern me, do I have to signal an interrupt...
 

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