Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
This is used to identify memory space range (memory space seen by host CPU). Even one device can have more than one function and one function can require more than one space range (this is allocated by host CPU at system boot-up and load the device driver). So, you root complex need BARs (not just one) to identify the memory space required by it's downstream device. This part is the same for both PCI and PCIe, you can refer to the PCI/PCIe doc for detail.
I have a Root complex connected directly with one End Point via PCIe link.
Root Complex BAR0 is programmed with 0x2000_0000, assume BAR range is of 64 KB that is 0x2000_0000 to 0x2000_FFFF
Root Complex BAR1 is programmed with 0x3000_0000, assume BAR range is of 64 KB that is 0x3000_0000 to 0x3000_FFFF
1} After link up to L0, End Point sends one Memory Write TLP with address 0x2000_0004 to the Root Complex. (Address of TLP falls in the BAR0 Range) What will happen?
2} After link up to L0, End Point sends one Memory Write TLP with address 0x4000_0004 to the Root Complex. (Address of TLP doesn't fall in the any of the BAR range) What will happen?
Hi, malav6789: maybe you have soem misunderstanding about the usage of the BARs. I'm familary with BARs defined in pci/pcie device(or endpoint).
In endpoint, when BAR0 is programmed with 0x2000_0000, assume BAR range is of 64 KB that is 0x2000_0000 to 0x2000_FFFF. That means that endpoint need 64KB memory sapce, and the host CPU allocated 64KB memory for that endpoint, the address range is 0x2000_0000 - 0x20000_ffff (this addree range is consumed by that endpoint). So, the host CPU can send r/w request to the endpoint within address range 0x2000_0000 - 0x2000_ffff (not the endpoint send out r/w request within the address range of 0x2000_0000 - 0x20000_ffff).
So, if the RC has the same mehcanism, then the two questions can be answered. You'd better refer to the PCI bridege or the PCIE RC Spec. for detail. The following is may suspect:
For 1): RC find this address has been occupied by that downstream endpoint and it can't pass this request up, to the upper RC or root.
For 2): RC find this address is not occupied by that downstream endpoint, the it will pass it to up, to the upper RC or root to decode the denstination of the request (also maybe dropped by upper RC or root).