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Hello,
I'm trying to define the required clearance through insulation for a power electronics multi-layer PCB. Following IPC 2221, a rather high internal conductor spacing of 0.75 mm would be required for 700 V working voltage (Table 6-1, column B1), applicable both for horizontal (same substrate surface) as well as vertical (through substrate) clearance.
There's of course a lot of concurrent standards, some add a differentiation between basic and reinforced insulation, e.g. ECMA-287 that requires no minimal isolation distance for basic and 0.4 mm for reinforced insulation (obviously sufficient dielectrical strength by design is presumed, too).
Compared to the detailed considerations in ECMA-287, the IPC rules seem not well founded and inappropriate at least for vertical clearance. Applying this rules, multilayer PCBs with HV between layers would be effectively banned, also many planar transformer applications.
I didn't pay attention to the design details, but I mean to remember having seen several electronic devices with HV PCBs that apparently ignore the IPC restrictions regarding vertical clearance.
I would be happy to hear some comments how others are dealing with this stuff.
Best regards, Frank
I'm trying to define the required clearance through insulation for a power electronics multi-layer PCB. Following IPC 2221, a rather high internal conductor spacing of 0.75 mm would be required for 700 V working voltage (Table 6-1, column B1), applicable both for horizontal (same substrate surface) as well as vertical (through substrate) clearance.
There's of course a lot of concurrent standards, some add a differentiation between basic and reinforced insulation, e.g. ECMA-287 that requires no minimal isolation distance for basic and 0.4 mm for reinforced insulation (obviously sufficient dielectrical strength by design is presumed, too).
Compared to the detailed considerations in ECMA-287, the IPC rules seem not well founded and inappropriate at least for vertical clearance. Applying this rules, multilayer PCBs with HV between layers would be effectively banned, also many planar transformer applications.
I didn't pay attention to the design details, but I mean to remember having seen several electronic devices with HV PCBs that apparently ignore the IPC restrictions regarding vertical clearance.
I would be happy to hear some comments how others are dealing with this stuff.
Best regards, Frank