[SOLVED] PCB Design: How fast data rates with pin headers?

[TommiRouvali]

Hi,

I designed PCB with Spartan 6 FPGA and my plan is to stack this board with other board having AD or DA converter (like AD9744). I was wondering how fast data rates are possible with pin headers like this: https://www.pololu.com/catalog/product/965 .(and female connectors matching it)

I know there is no simple answer, it depends on line impedances, connector quality, driver and receiver properties and so on. But I imagine someone with more experience can say is 50Msps, 100Msps or 200Msps I can use to drive DA converter?

 

[FvM]

200 MSPS isn't a problem with 0.1" headers as such, but for the present development board, single ended IO without sufficient ground connections will result in poor signal quality.

 

[rfmw]

What you need to do is to "slow-down" the drivers of your digital signals. In other words, if you can, set the rise/fall times of your drivers to a maximal value for your digital bitrate. If possible, use differential signaling instead of single ended ones.

 

[TommiRouvali]

FvM: So you suggesting I should add more ground connections to headers. For example each other pin, or at least few to center?

If you were referring to bottom layer ground plane(blue), there are 0 ohm resistors to make ground more solid.

 

[FvM]

So you suggesting I should add more ground connections to headers. For example each other pin, or at least few to center?

Yes.

If you were referring to bottom layer ground plane(blue), there are 0 ohm resistors to make ground more solid.

I'm referring to the pin header assignment. Feasibility of 200 MSPS FPGA-IO on a two-layer PCB is beyond the original question, I think.

I'm not so familiar with Xilinx FPGA, but generally I would rate it as experimental layout, with a certain chance to get it working.