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PCB based Antenna Match measurement

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Mar 22, 2022
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Good morning all,
Sorry if I'm reposting a question that's been done over and over.. but I'm testing a piece of customer equipment with WLAN capability in my current contract. The WLAN chipset is on a main PCB, printed antennas on little PCBs are mounted on the plastic front panel. Antenna PCBs have a U.FL pigtail and connect to the main board U.FL socket. The engineer who designed the board has put on another U.FL socket with an arrangement of FIT/NoFIT resistors so that the S11 into the antenna can be measured... however he's calibrating the VNA tail with an SOLT, then using a SMA to U.FL to connect into the board on the "test" U.FL socket to measure the match to the antenna connected to the second socket. There are pads for matching components between the chipset and the antenna U.FL socket.
In previous lives I've always tried to copy bits of critical layout like this, plus a Short, Open and Load, onto a test coupon with a edge mounted SMA, or, if that's not been done, used either a little bit of thin semi-rigid to launch from the VNA straight onto the WLAN chip output pads, or used a Gigatest Labs station.
That way, the VNA correction can be done using the Gigatest SOL boards, or by making up semi-rigid launchers on to a bit of PCB / coupon populated with components make up SO & L. My thought is that what's going on here with this second U.FL is completely skewing the measurement by introducing additional length and discontinuity into the RF train. However I appreciate that I don't have the luxury of a Gigatest probe station here, and I don't get a perfect SOLT correction making up my own standards so errors will be introduced there.
I've attached a shonky MSPaint image of what's going on at the main PCB, sorry about the quality but it gives the general idea.
I'd love to hear your thoughts as the best way to get a meaningful baseline measurement with correction at a defined reference plane with what I have around me, so that I can get on to working out the matching network.


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Well, a day of working on it has moved things forward. I've dismissed the additional U.FL ports as neither use nor ornament. I performed a single port SOL correction at the end of my PNA lead, subtracting my SMA-RG405 launcher through the port extension function and attached the launcher to the ANT OUT pads on the chipset footprint. Then I've just added L & C elements as I go along (calculating on the smith chart then tuning empirically) to get a (broadly) minimum-Q match network with a handful of components. My antenna minimum now sits nicely where it should... I just need to do apply the mod to a board with a WLAN chipset on it and do some swept CW testing in the chamber. I hope I'm doing this right.

In similar antenna measurements, I found it practical to calibrate the VNA with pigtail for a reference plane at the U.FL connector, using self-elaborated U.FL SOL adapters.

The more demanding problem in this setup is to eliminate cable effects by the VNA connection, i think.

My thought is that what's going on here with this second U.FL is completely skewing the measurement by introducing additional length and discontinuity into the RF train.

This type of setup is used often, and should work sufficiently well.

To evaluate and match antenna in Smith chart, you would indeed remove the extra length caused by the U.FL cable. A simple approach would be to leave it open and determine phase offset from this "open" measurement.

If you suspect mismatch from cable or the extra connector, you could re-jumper PCB components to have 50 Ohm shunt (instead of the antenna) in the matching component section.

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