PC - Fpga communication protocol

[myms]

Hi,

I am a newbie in FPGA environment. Kindly need any help about my problem.

I need to know how the communication between FPGA and PC. Recently, i designed some verilog code that need to download in FPGA board through serial port from PC. FPGA received and processed the command and send back to PC.

At this point, there will be a parallel activity happen : the PC will received and display the output get from FPGA while the FPGA executed the command earlier. I am doubt about FPGA, what will happen after executed? if it still executing the command until i turn off the board?

Same case if i use "halt" command, FPGA will halt using the cpu clock and then what will happen? how can i determined whether the process in FPGA are halt or still running?..please help me..i need to understand this to overcome my problem because currently, there was an error if i use sdk in my design.

please help explain to me. Thanks in advance. Much appreciated all your effort.

Rgds,
myms

 

[prakashvenugopal]

Hi,

Place one counter and out the Q output everytime to the Port Pin connected to the LED. Apply the Base Oscillator clock to the counter clock.Always Enable the counter.

What tool are you using? Are you using EDK for the communication between PC and FPGA or just using ISE? or ISE + EDK?