passing clocks to 2nd fpga

[stevepre]

Suppose we need a design with clk in one FPGA, and we also need this clk to go to 2nd fpga, and the skew between them must be small.

What's the best way to achieve this?

Thanks

 

[keano]

Hi,

I think that you should connect the two FPGAs to the same quartz (which generates the clock).

I'm not very sure of my answer, I'm going to ask the guys at work but you have to wait till monday

 

[gliss]

You can connect both FPGAs to the same clock. It's more of a board design issue than anything else I imagine.

 

[keano]

You can connect both FPGAs to the same clock. It's more of a board design issue than anything else I imagine.

Yep that's right

 

[stevepre]

Thanks guys.

However, I don't think the problem is that easy.

Basically, a lot of times, a board can have certain frequency in. For example, 20MHz.

Inside the first FPGA, there's advanced DCM to make the clock higher frequency, let's say, 80MHz.

Now the problem is, if we want to pass this 80MHz to the 2nd FPGA, while making these 2 80MHz clock in sync, we need to do some de-skewing.

I need to know exactly what kind of de-skewing we can do to have the minimal skew between these two clocks so that they can be synchrnous to each other.


Thanks

 

[eject]

1/ high-freq in PCB might cause EMI
2/ Which one you want to improve, jitter or long-term jitter ?

 

[bansalr]

Actually U can pass on the 80 Mhz from one FPGA to another but there will be a skew and if u r exchanging the data back and froth between two FPGA then u may encounter a serious problem with skew.

Because PAD delay are significant.

Other way is to use the same oscillator and generate the clock in both the FPGA's independently with same source and use FIFO to seperate the clock domain when using the other FPGA clock or use negedge to have a half period margin.

Added after 51 seconds:

Actually U can pass on the 80 Mhz from one FPGA to another but there will be a skew and if u r exchanging the data back and froth between two FPGA then u may encounter a serious problem with skew.

Because PAD delay are significant.

Other way is to use the same oscillator and generate the clock in both the FPGA's independently with same source and use FIFO to seperate the clock domain when using the other FPGA clock or use negedge to have a half period margin.

 

[Iouri]

NOw question is: WHY??/ I assume, if you have data to transfer from one FPGA to another. Yes you can run clock trace from one FPGA to another, concideration should be taken about PCB layout, and way how you impplimenting input stages...

Good Luck