partially floating nwell problem..

[rookie1986]

Hi~

I finished tape out but I found some problem..

I used bunch of PMOS inside opamp [ from vdd- tail current (PMOS) - diffpair(PMOS) mirror load (NMOS)] and I merge all the PMOS (actually nwell) together to save area..

Among the entire nwell area about 80% have a strong vdd nwell contact.

But some region about the size of 40 um by 20um [diff pair pmos], even though I made "nwell contact" around boder line of nwell, I forget to connect this "nwell contact" to main nwell contact.

So, some part of NWELL is floating. (more accurately, it is connected with nwell resistor, that`s why it can`t captured by LVS]

LVS just shows matched, but actually after I click ok it shows some" stam and mult error", but I didn`t click ok at that time after pass LVS...

How much this kind of floating nwell region affect the performance?

fortunately, floating n well contact metal may reduce the nwell resistance and I put all the psub contact around it. [no latch up DRC error].

I worry about it please give some feed back on this..

 

[erikl]

You badly need nwell contacts close to all PMOS' sources, otherwise you risk latchup - which isn't seen by DRC rules, because these check latchup rules just for min. and max. spacing.

It's just a small risk, but I wouldn't allow for it - you'd think about it all the time waiting for the protos. Repair, one more DRC run and tapeOut is quickly done after all, only a few more hours.

Just my suggestion.