partial place and route - how to reduce sysnthesis and place

[siddharth3]

partial place and route

Hello all,
I have been implementing a design on a Xilinx FPGA for a few weeks. Since the rtl is huge it takes arnd 5hrs for synthesis and place and route to complete(1hr+4hr). Everytime there is a small change in the RTL, the whole process needs to be redone and it consumes a lot of time. Is there a way in which i can reduce sysnthesis and place and route time by concentarting on just the block that was changed??? please help me...

 

[raka200]

partial place and route

Hi !!
If you use ISE, there is a partition option. The partition mode allow you to synthesis only the partition that is modified. But the place and route start from nothing.
I design on xilinx fpga, and the first thing I do is to divide the design in several independant modules.
I create some code to generate the input for each modules, so that I could synthesis and PAR only the module under test. For FPGA, it takes you 1 hour to write the code, and 3 hours to write the testbench and check that your code is correct....

Regards,