parse error with function in vhdl.

[talhaelex]

I just want to write a vhdl code for switch matrix to switch the output of the 8:1 mux between five different blocks in specific manner,for that i ave written the following code but at the time of 1st iteration it is showing parse error, unexpected FUNCTION.please help me in this regard.My code is :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux is
port(A,B,C,D,E:in std_logic_vector(5 downto 0);
s:in std_logic_vector(2 downto 0);
yut std_logic_vector(5 downto 0) );
end mux ;

architecture Behavioral of mux is
-- 8:1 MUX
begin
process(s,A,B,C,D,E)
begin
case s is

when "000"=>y<=A;
when "001"=>y<=B;
when "010"=>y<=C;
when "011"=>y<=D;
when "100"=>y<=E;
when others =>y<="000000";
end case;
end process ;

-- FUNCTION FOR SWITCH MATRIX

function o_p(signal s0,s1,s2,s3,s4:std_logic_vector(5 downto 0))
return :std_logic_vector(5 downto 0)is

begin
type reg_array is array(5 downto 0)of std_logic_vector(5 downto 0);
signal s0:reg_array;
signal s1:reg_array;
signal s2:reg_array;
signal s3:reg_array;
signal s4:reg_array;

for i in 0 to 5 loop
s0(i)<=s4(i);
s1(i)<=s0(i);
s2(i)<=s1(i);
s3(i)<=s2(i);
s4(i)<=s3(i);
end loop;
return s0,s1,s2,s3,s4;
end o_p;

-- FUNCTION FOR BUFFER
function op_buffer (signal t0,t1,t2,t3,t4 :std_logic_vetor(5 downto 0))
return std_logic_vetor(5 downto 0)is
signal R:std_logic_vetor(5 downto 0);
variable counter:std_logic_vetor(4 downto 0);
begin
if (counter ="11001")then
y<="000000"
else
case R is

when ( R=t0 )=> s0;
when ( R=t1 )=> s1;
when ( R=t2 )=> s2;
when ( R=t3 )=> s3;
when ( R=t4 )=> s4;
end case;
return s0,s1,s2,s3,s4;
end op_buffer;

-- FUNCTION CALL


G0 <=op_buffer(A,B,C,D,E);
OP0<=o_p(s0,s1,s,s3,s4);
counter=counter+1;

G1 <=op_buffer(B,A,C,D,E);
OP1<=o_p(s0,s1,s,s3,s4);
counter=counter+1;


G2 <=op_buffer(A,C,B,D,E);
OP2<=o_p(s0,s1,s,s3,s4);
counter=counter+1;


G3 <=op_buffer(A,B,D,C,E);
OP3<=o_p(s0,s1,s,s3,s4);
counter=counter+1;


G4 <=op_buffer(A,B,C,E,D);
OP4<=o_p(s0,s1,s,s3,s4);
counter=counter+1;



end Behavioral;

 

[FvM]

You have mixed architecture declarative and statement part. Review a VHDL text book or the IEEE 1076 LRM for the required order.