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parse error unexpected variable

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p11

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Code:
---------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:38:49 05/13/2015 
-- Design Name: 
-- Module Name:    COUNTLED - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std .all;
package my_package is

function add (signal p,q : integer )  return integer ;

end package ;

package body my_package is 

function add ( signal p,q : integer ) return integer is 

begin

return p+q;

end add;

end my_package ; 



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use work . my_package .all;
entity add_1 is

port (a: in integer ;
      b : in  integer ;
		
		y : out std_logic);

end  entity add_1;	


architecture beh of add_1 is 

begin 

 variable c: integer ;..................... line 63 
 
begin 

c:= add (a,b ) ;

 if c= 5  then 
 
 y <='1';
 else
 
 y <='0';
 
 end if;
 
end  beh



ERROR:HDLParsers:164 - "C:/Users/user/Desktop/phd/xilinx/p1/p11.vhd" Line 63. parse error, unexpected VARIABLE
 
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TrickyDicky

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You cannot declare a variable inside an architecture. You can only put variables inside processes, functions and procedures.
You also have a problem because you have conditional code outside of a process.
 

p11

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will u plz correct my code and post it .
 

TrickyDicky

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If I did your work for you, you wouldnt learn.
Why not try modifying it yourself and trying again.
It sounds like you need to read a VHDL tutorial.
 

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