Parse error, unexpected identifier

[PRIYA_]

HELLO FRENS
IM WORKING ON SPARTAN 3A KIT.
THIS IS MY CODE FOR SERIAL COMMUNICATION.

---

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----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:25:14 05/02/2012 
-- Design Name: 
-- Module Name:    MyDesign - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
   Entity UART is
  Port (  CLKIN     : in  std_logic;  -- System Clock at Fqxtal
          RST       : in  std_logic;  -- Asynchronous Reset active high
             LOAD      : in  std_logic;  -- Load, must be pulsed high
          Tx        : out std_logic;  -- Serial data out
          TxBusy    : out std_logic;  -- '1' when Busy sending
             BAUD_CLK  : OUT STD_LOGIC
       );
end UART;
 
-- ---------------------------------------------------------------
    Architecture RTL of UART is
-- ---------------------------------------------------------------
 constant Fxtal  : integer  := 50000000; -- in Hertz
 constant Parity : boolean  := false;
 constant Even   : boolean  := false;
 constant Baud1  : positive := 115200;
 constant Baud2  : positive := 19200;
--SIGNAL Baud    : std_logic := '0';
 
function myMin ( i, j : integer) return integer is
begin
  if i <= j then return i; else return j; end if;
end function;
 
constant Debug : integer := 0;
constant MaxFactor : positive := Fxtal / MyMin (Baud1,Baud2); -- 2604
 
constant Divisor1 : positive := (Fxtal / Baud1) / 2; -- 217
constant Divisor2 : positive := 1302;
 
Type TxFSM_State is (Idle, Load_Tx, Shift_TX, Parity_Tx, Stop_Tx  );
signal TxFSM : TxFSM_State := Idle;
 
signal Tx_Reg : std_logic_vector (8 downto 0);      -- Transmit register
signal TxDivisor: integer range 0 to 2604;          -- Tx division factor 0 to 2604
signal TxDiv : integer range 0 to 2604;             -- Transmit clock generation register 0 to 2604
signal TopTx : std_logic;                                   -- Transmit master clock pulse
signal TxBitCnt : integer range 0 to 15;
signal Tx_Par  : std_logic;                                 -- Transmit parity bit
signal Din     : std_logic_vector (7 downto 0); 
 
 
type array1 is array (0 to 7) of integer;
signal  arr : array1 := (1,1,1,1,1,1,1,1);
 
signal x : integer RANGE 0 TO 1200000000;
signal a1,a2,a3,a4,a5,a6,a7,a8,a9,a10 : integer range 0 to 9 ;
 
constant v : real := 19.6 ;
x <= arr(0) + arr(1)*v + arr(2)*(v**2) + arr(3)*(v**3) + arr(4)*(v**4) + arr(5)*(v**5) + arr(6)*(v**6) + arr(7)*(v**7);  --parse error, unexpected identifier
a1 <= x rem 10;
a2 <= a1 rem 10;
a3 <= a2 rem 10;
a4 <= a3 rem 10;
a5 <= a4 rem 10;
a6 <= a5 rem 10;
a7 <= a6 rem 10;
a8 <= a7 rem 10;
a9 <= a8 rem 10;
a10 <= a9 rem 10;
 
TYPE VOLT_STATE IS  (ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN);
SIGNAL VOLT : VOLT_STATE := ONE;
 
--------
begin
--------
TxDivisor <= 2603;   
 
-- --------------------------
--  Tx Clock Generation
-- --------------------------
-- Periodicity : bit time (runs continously)
 
process (RST, CLKIN)
begin
  if RST='1' then
    TxDiv <= 0;
    TopTx <= '0';
  elsif rising_edge(CLKIN) then
    TopTx <= '0';
    if TxDiv = TxDivisor then -- 115207Hz (0.000061 % deviation)
      TxDiv <= 0;
      TopTx <= '1'; -- This pulse is for one CLK period (20ns)
    else
      TxDiv <=  TxDiv + 1;
    end if;
  end if;
end process;
BAUD_CLK <= TopTx;
 
-- --------------------------
--   VOLTAGE STATE MACHINE
-- --------------------------
 
PROCESS (TopTx)
BEGIN
if rising_edge(TopTx) then
CASE (VOLT) IS
 
    WHEN ONE =>
            Din <=  X"3" & a1;
            VOLT <= TWO;
    
    WHEN TWO =>
            Din <=  X"3" & a2;
            VOLT <= THREE;
            
    WHEN THREE =>
            Din <=  X"3" & a3;
            VOLT <= FOUR;
            
    WHEN FOUR =>
            Din <=  X"3" & a4;
            VOLT <= FIVE;
            
    WHEN FIVE =>
            Din <=  X"3" & a5;
            VOLT <= SIX;
 
    WHEN SIX =>
            Din <=  X"3" & a6;
            VOLT <= SEVEN;
            
    WHEN SEVEN =>
            Din <=  X"3" & a7;
            VOLT <= EIGHT;
            
    WHEN EIGHT =>
            Din <=  X"3" & a8;
            VOLT <= NINE;
            
    WHEN NINE =>
            Din <=  X"3" & a9;
            VOLT <= TEN;
            
    WHEN TEN =>
            Din <=  X"3" & a10;
    
    WHEN OTHERS =>
            VOLT <= ONE; 
 
END CASE;
END IF;
END PROCESS;
 
 
 
-- --------------------------
--  TRANSMIT State Machine
-- --------------------------
 
TX <= Tx_Reg(0); -- LSB first
 
Tx_FSM: process (RST, CLKIN)
begin
  if RST='1' then
    Tx_Reg   <= (others => '1'); -- Line=Vcc when no Xmit
    TxFSM    <= Idle;
    TxBitCnt <= 0;
    TxBusy   <= '0';
    Tx_Par   <= '0';
 
  elsif rising_edge(CLKIN) then
 
    TxBusy <= '1';  -- Except when explicitly '0'
 
    case TxFSM is
 
      when Idle =>
          if LOAD='1' then
            Tx_Reg <= Din & '1'; -- Latch input data immediately.
            TxBusy <= '1';
            TxFSM <= Load_Tx;
          else
            TxBusy <= '0';
          end if;
 
      when Load_Tx =>
          if TopTx='1' then
            TxFSM  <= Shift_Tx;
            Tx_Reg(0) <= '0';    -- Start bit
            TxBitCnt <= 9;
        
            if Parity then       -- Start + Data + Parity
              if Even  then
                Tx_Par <= '0';
              else
                Tx_Par <= '1';
              end if;
            end if;
          end if;
 
      when Shift_Tx =>
          if TopTx='1' then     -- Shift Right with a '1'
            TxBitCnt <= TxBitCnt - 1;
            Tx_Par <= Tx_Par xor Tx_Reg(1);  -- <<< error in v4.0 fixed in v4.1
            Tx_Reg <= '1' & Tx_Reg (Tx_Reg'high downto 1);
            if TxBitCnt=1 then
              if not parity then
                TxFSM <= Stop_Tx;
              else
                Tx_Reg(0) <= Tx_Par;
                TxFSM <= Parity_Tx;
              end if;
            end if;
          end if;
 
      when Parity_Tx =>       -- Parity bit
          if TopTx='1' then
            Tx_Reg(0) <= '1'; -- Stop bit value
            TxFSM <= Stop_Tx;
          end if;
 
      when Stop_Tx =>         -- Stop bit
          if TopTx='1' then
            TxFSM <= Idle;
          end if;
 
      when others =>
          TxFSM <= Idle;
 
    end case;
    end if;
    end process;
 
end RTL;

---

I AM TRYING TO CONVERT THE BIT PATTERN '11111111' (WHICH IS RECEIVED FROM THE ADC ) INTO THE CORRESPONDING VOLTAGE VALUE.

EVERY TIME I TRY TO RUN THE PROG AN ERROR COMES "PARSE ERROR, UNEXPECTED IDENTIFIER" IN LINE NO.82
THIS ERROR ARISES ONLY IF THERE IS A SYNTAX ERROR. BUT I AM NOT ABLE TO FIGURE IT OUT WHERE IS THAT SYNTAX ERROR....

MOREOVER WHEN I MAKE THAT LINE(LINE 82) A COMMENT THE SAME ERROR SHIFTS TO THE NEXT LINE (LINE 83)

PLEASE HELP..... I REALLY NEED TO FIND THE ANSWER ASAP...

 

[TrickyDicky]

you need to move those assignments to x and a1-10 after the "begin" part of the architecture. Before the begin is just for declarations.

 

[PRIYA_]

Thank u tricky..
But there is still some problem...
I mean this error has been solved but now the errors r coming as follows
& cant have such operands in this context
these errors r coming in the voltage state machine

* cant have such operands in this context
this errors is coming in the assignment statement where im assigning my value to x

please help me..... I have very little time to complete this
plzzzzzzzzz