Parameters of NMOS and PMOS in 45 nm CMOS technology

[whirl7wind77]

Where can I find/What are the parameters of NMOS and PMOS ( like VTno, VTpo , Kn , Kp ) in 45 nm CMOS technology ?

[By simulation I found that VTn is approx. 0.4-0.5V . Is it not too high ? ]

 

[Dominik Przyborowski]

The device parameters in the same technology node differ from foundry to foundry. If You have pure digital process, probably You have only low power devices with quite high threshold voltages ~0.5V. Analog/RF processes has transistors with various Vth like zero (~50mV), low Vth (~100mV), normal (~200mV) and low power with high Vth.

You need to found process documentation which should be provided with your pdk.

 

[whirl7wind77]

1)Where can I locate PDK i.e., documentation ?
2)I could find in my library a variety of 1V nmos transistors like nmos1v,nmos1v_lvt,nmos1v_hvt,nmos1v_nat, nmos1v_lvt_3, nmos1v_hvt_3, nmos1v_nat_3.
Does 3 at the end mean a 3-terminal device (which means probably a zero Vt) ?

 

[Dominik Przyborowski]

I don't know your process, but if it is a bulk CMOS probably the devices ending with "3" are triple well fets with 6 terminals. Your pdk provide devices with 3 different threshold voltages. _lvt for lower, _hvt for higher Vth and standard ones. I don't know what _nat means but it could be the same as standard fet.

To found your PDK location check the models path.

 

[whirl7wind77]

I found the model library file i.e., ......045_mos.scs . I searched for vth0 , u0 , toxe . There are too many results. Which one is the correct one ?

 

[Dominik Przyborowski]

If You are using Cadence Virtuoso environment, run ADE L. In ADE L→Setup→Model Libraries. Sometimes full path is in ADE L→Setup→Simulation Files.

Unfortunately I never used other software than cadence, so I'm helpless with mentor graphics or synopsys tools.

 

[whirl7wind77]

Thanks. But I find it before your post with your previous hint. I found the model library file i.e., ......045_mos.scs . I searched for vth0 , u0 , toxe . There are too many results. Which one is the correct one ?

 

[fredd]

you can check for every transistor model, there should be a corresponding vth0.

 

[erikl]

I don't know what _nat means but it could be the same as standard fet.

_nat very probably stands for a native MOSFET, which has a very low Vth (guess 50..100mV). Disadvantage is a relatively high leakage current when off (Vgs=0).

 

[whirl7wind77]

I could find in my library that there is nmos1v_nat but no pmos1v_nat.
Why is that ?

 

[erikl]

I could find in my library that there is nmos1v_nat but no pmos1v_nat. Why is that ?

_nat transistors need one more mask + implant, for each transistor type. From design considerations, nmos natives are far more often used than pmos nats. So, for some processes, this latter option isn't offered to reduce costs.

 

[an_82]

If you use Hspice, .list file could be helpful to find that parameters.