[SOLVED] Parameters like speed, area and power after dumping on FPGA board

[rafimiet]

I have a design that I have implemented in Vivado and also I have extracted the parameters (area, speed and power) from Vivado. Now as I dump the code on Zedboard, it provides me with the functional behavior of my design on actual board. Is there any way-out to find the same parameters from the board itself, when the design is running on the board? Is there any difference between the parameters extracted from post-place-and-route synthesis and design actually running on board itself?

 

[vGoodtimes]

speed is only accurate if the input clocks match the specified clocks.

power is only an estimate. It is highly affected by actual data running through the design.

area is accurate.

 

[rafimiet]

speed is only accurate if the input clocks match the specified clocks.

power is only an estimate. It is highly affected by actual data running through the design.

area is accurate.

So, you mean area need not be checked after dumping the design. Can I somehow extract the parameters from the board?

 

[TrickyDicky]

So, you mean area need not be checked after dumping the design. Can I somehow extract the parameters from the board?

No - for power you need to measure the power with a power meter/ammeter
Not sure exactly what you mean by "speed". The clock frequency will be fixed in the design, so you already know what the clock speed/data rate is.

 

[rafimiet]

for power you need to measure the power with a power meter/ammeter

The voltage supplied to the board remains the same, so we have to find the current that goes into the board and multiply the two. Is that how to find out power?

Not sure exactly what you mean by "speed".

I mean the total time to process a block of data. Will it remain the same for PAR and dumped design?

area need not be checked after dumping the design.

Does it mean, area optimization after PAR is same as that used practically by FPGA board?

 

[TrickyDicky]

The voltage supplied to the board remains the same, so we have to find the current that goes into the board and multiply the two. Is that how to find out power?

yes, its pretty easy to determine the board power. Much more difficult for individual components.

I mean the total time to process a block of data. Will it remain the same for PAR and dumped design?

yes, and this is something you should already know from your architecture/simulation results. It has nothing to do with Xilinx tools. Processing time is down to your design choices.

Does it mean, area optimization after PAR is same as that used practically by FPGA board?

Your compiled design has all luts and routing already placed. This is what gets programmed to the chip. None of this changes during runtime (that would be like adding/removing components to a pcb while it was running).

 

[vGoodtimes]

Power is the hardest to measure. In some applications, large parts of the design are inactive most of the time in many applications. Power depends more on a knowledge of the application and the wworst case.

Time to process a block should be very close to simulation, ith only simulation frequency mismatches as an issue. This should mostly be a non-issue in most cases.

Area is basically what is in your design. I could potentially find a way wwhere the results ould be different, but not where you would not know why.

(typed on a broken keyboard)