Because as I've told you before, a software paradigm doesn't fit with how you write code for HDLs.
FOR loops are unrolled spatially not sequentially, i.e. for loop are used to replicate logic (spatial) not set the order of events (sequuence). You use an FSM to keep track of the ordering of events.
As I've mentioned previously, draw the circuit that does what you want (don't write HDL until you know how to design the circuit) then translate that circuit to an HDL. If you do it this way you will understand what the HDL is going to produce when synthesized.