Parameter as bit width in verilog CONSTANT

[imbichie]

Hi all,

How we can use the parameter as bit width in verilog for a CONSTANT value representation.
For example :

parameter VAL = 11;
always @ ( posedge CLK or negedge RESETn )
  begin
    if ( !RESETn )
      begin
        count <= {VAL{1'b0}};
      end
    else
      begin
        if ( count == [B][COLOR="#FF0000"]11'h5FF[/COLOR][/B] )
          begin
            count <= {VAL{1'b0}};
          end
        else 
          begin
            count <= count + [B][COLOR="#FF0000"]11'h1[/COLOR][/B];
          end
      end
  end

So here instead of 11'h5FF and 11'h1, how I can replace this with parameter VAL.

 

[dave_59]

11'h5FF can be replaced with {VAL{1'b1}}. {n{M}} means concatenate the replication of M, n times.

There is no need to size operands to get 0's extended, Verilog does this automatically

parameter VAL = 11;
always @ ( posedge CLK or negedge RESETn )
  begin
    if ( !RESETn )
      begin
        count <= 0;
      end
    else
      begin
        if ( count == {VAL{1'b1}} )
          begin
            count <= 0;
          end
        else 
          begin
            count <= count + 1;
          end
      end
  end

 

[imbichie]

11'h5FF can be replaced with {VAL{1'b1}}. {n{M}} means concatenate the replication of M, n times.

Hi Dave thank you for your reply.

But i think 11'h5FF -> 11'b101_1111_1111
so it cannot be {11{1'b1}} -> 11'b111_1111_1111
so here {VAL{1'b1}} means its 11'h7FF not 11'h5FF.

 

[dave_59]

Sorry, my mistake

Then what are you looking to do with the parameter VAL? It is not need with the code that you have shown.

 

[imbichie]

Hi dave,

The thing is that i need to replace the 11 with VAL in this representation 11'h5FF,
means something like VAL'h5FF ( <- this is wrong)

 

[dave_59]

But why not just do

'h5FF

Verilog will pad 0's to the left to fill count.