Hi I have a voltage shunt regulator with moderate current (1-2A) where I use two mosfet in the buffer stage in linear mode to regulate the output voltage. To compensate for the potential mismatch and drift of the inherent parameters of the mosfets (gm & vth) I have added a ballast resistor (0.3R) at source terminal in each device to help with the current sharing and it seems to work well in real application. However the chosen value was a bit random and I´d like to use a more professional approach, is there any rule of thumb or theoretical procedure on how to dimension this ballast resistor to equalize currents ?
(the mosfet is very likely to be operating with very low VGS , i.e. below ZTC (zero temperature coefficient)
Almost any value will work to some degree but to be absolutely sure of reaching equal currents the voltage dropped across the resistor should be equal to the difference in gate thresholds. You can find the upper and lower limits from the data sheet although they will quote extreme cases, in practice the differences are likely to be closer to the center value. Above threshold both will be in conduction so the values are less relevant.
A question is, do you need actual equality of current sharing
and if so, where?
If you are only addressing ratings / thermals, you then care
only about the "big end" and low value resistors (if any) are
all you need.
I've seen it said that the FETs' ID tempco gives a tolerable
degree of anti-hogging (unlike BJTs). You can see in FET
I-Vs, pulled in poor thermal conditions, that the ID@Vds
declines across the pull rather than rising - it's all thermal
(mobility degradation).
See page 5-16 for schematics using bjt's. (We can guess mosfets are similar.)
It appears you are correct to use the source leg for the resistor. Current through the resistor creates voltage across it. Increased Amperes causes increased volts. The net effect is to change bias-emitter voltage, by reducing it thus reducing transistor conductivity.
This principle of regulation does not occur if using the drain (collector) leg.
Most application notes are only discussing parallel connection in switching mode. Only NXP AN11599 has a small paragraph about linear operation.
In linear mode, initial Vgs,th variation is the major source of current imbalance. Unless you are pairing transistors for matched Vgs, balancing source resistors are always required.
Minimal source resistor value will be mainly commanded by the expectable Vgs,th range. Negative Vgs TC demands a certain increase of Rs.
You should also consider that most power MOSFET have reduced SOA in linear operation because they don't achieve an uniform current distribution over die area.
Like FvM mentions above, beware guidelines aimed at switching applications. Completely different considerations than linear operation.
A more methodical approach requires knowing something about the distribution of MOSFET parameters you will see. Hopefully the datasheet provides a min/max spec for threshold voltage and Gm.
IntroductionWhile it is often desirable, and sometimes absolutely critical, to use multiple parallel MOSFETs in Hot Swap™ circuits, careful analysis of Safe Operating Area (SOA) is essential. Each additional parallel MOSFET added to a circuit improves the voltage drop, power loss, and...