parallel chain and scan simulation

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palanis29

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dft simulation error debugging

hi,

am new to dft field, i did simulation chain & scan, chain passed, but in scan simulation parallel passed but serial is failing. pls help me to fix this.

thanks & regards,
palani
 

Re: dft simulation error debugging

Hi,

How can we help....without any details about your project?

Klaus
 
Re: dft simulation error debugging

what is the meaning of 'dft simulation'? are you doing gate-level simulation of a design that contains a scanchain?
 
Re: dft simulation error debugging

what is the meaning of 'dft simulation'?
Click to expand...
I think the OP is talking about simulating a scan-chain inserted design by using test-patterns generated by an ATPG tool.
But I think he/she is too naive to explain what has actually been done and what is the target intention.
 
Re: dft simulation error debugging

is there is any logic reason is there????
 

Re: dft simulation error debugging

As told in #2, without more info no one can help you.

am new to dft field, i did simulation chain & scan, chain passed, but in scan simulation parallel passed but serial is failing. pls help me to fix this.
Click to expand...
We don't know your design and intention, so how can a fix be suggested?

Also please write proper short sentences so that we can decode it without difficulty.
This is for your benefit: http://www.catb.org/esr/faqs/smart-questions.html
 
how the parallel chain & parallel scan simulation works?
 

palanis29 said:
how the parallel chain & parallel scan simulation works?
Click to expand...
Hello, Actually, I don't know about your issue in detail.
I guess that scan simulation you mentioned is pattern validation process using simulation tool(such as NC-verilog, VCS..)
Serial simulation is more similar as real-case that parallel simulation.
So, I guess It's not real fail..
Please check force & release time at testbench.
 

palanis29 said:
how the parallel chain & parallel scan simulation works?
Click to expand...

Parallel pattern means you forcing in scan shift and focus on capture cycle only.
Chain or sample pattern means this kind of pattern is real ( shift in/out from/to IO)

For example in your design the maximum chain length is 100 this mean :
Parallel only costs 1x2 shift cycle + 1 capture cycle -> boost up simulation time only
Serial costs 100x2 shift cycle + 1 capture cycle
 

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