PAR successfull, simulation fails

[thepiper]

par simulation fails

Hello everyone, I'm using ise 9.2i for my design, and PAR runs successfully and meets all my constraints with no timing errors, but when i run the simulation, it reports multiple warnings of all kinds (hold/setup violation...), what could be the problem?

 

[thiagu_comp]

This is possible. For example, if there is reset recovery / removal issue, this cant be found unless the specific timing for the signal is captured in the timing constraint. There is a possibility that your reset in testbench, violates this timings and a warning is generated. Can you please explain what constraints have you provided for timing and what are the violations?

 

[thepiper]

my constraint are just the basic period and offset constraints, and the warnings are
X_FF PULSE WIDTH High VIOLATION ON RST;
X_FF HOLD X VIOLATION ON I WITH RESPECT TO CLK;
X_RAMB16_S9_S9 HOLD High VIOLATION ON DIA(7) WITH RESPECT TO CLKA;
X_RAMB16_S9_S9 SETUP High VIOLATION ON DIA(6) WITH RESPECT TO CLKA;

 

[shanmugaveld]

Pulse width violationon rst may occur if ur reset pulse may be very smaller than to detect the reset. Increase the pulse width of ur reset..

for the violation
"HOLD High VIOLATION ON DIA(7) WITH RESPECT TO CLKA" check the below link.
**broken link removed**