Papers about designing hierarchical FSM

[davyzhu]

Hi all,

I am new to hierarchical FSM design.
Is there any paper or guideline for design hierarchical FSM?

Any suggestions will be appreciated!
Best regards,
Davy

 

[bajahaya]

Re: Hierarchical FSM?

https://www.eventhelix.com/RealtimeMantra/HierarchicalStateMachine.htm

Hope this shld be useful

Rdgs,
ALI

 

[omara007]

Re: Hierarchical FSM?

http://www.eventhelix.com/RealtimeMantra/HierarchicalStateMachine.htm

Hope this shld be useful

Rdgs,
ALI

This is more into software programming .. is there anything related to digital design / RTL (VHDL or Verilog) ?

 

[ljxpjpjljx]

Re: Hierarchical FSM?

you want an example or syntax ?

 

[omara007]

Hierarchical FSM?

I already have a hierarchical FSM in my design and I want to know the best RTL (VHDL/Verilog) coding style.

 

[pmat]

Re: Hierarchical FSM?

Hi,
have a look at Smith's book. There is a chapter on FSMs and some
paragraphs on different coding of hierarchical FSMs. Page 242 :
https://www.scribd.com/doc/7307641/HDL-Chip-Design-Using-VHDL-or-Verilog-Douglas-J-Smith-Part-2

Hope it helps,

Pavlos

 

[omara007]

Re: Hierarchical FSM?

Hi,
have a look at Smith's book. There is a chapter on FSMs and some
paragraphs on different coding of hierarchical FSMs. Page 242 :
https://www.scribd.com/doc/7307641/HDL-Chip-Design-Using-VHDL-or-Verilog-Douglas-J-Smith-Part-2

Hope it helps,

Pavlos

Thanks pmat .. I will read this chapter and get back to you for further details ..

 

[bapodradhairyab]

Hierarchical FSM?

Generally for making hierarchical FSM some output is passed and input is taken from other FSM to change state and output from that perticular state is enable for FSM inside that state. We define different module for internal FSM and call it as submodule in top module thate is FSM

example:
supposse your for states are S0, S1,S2 and S3

in S0 some state machine that generates sequence 00-01-11-10
in S1 sequence 00-10-11-01

and so on....

you can pass signal en_s0 for starting module that contains FSM to generate corresponding sequence and for that it use one more FSM...

and so on...

Hope you have clear up to some point...

 

[omara007]

Hierarchical FSM?

The problem here is about the definition of hierarchical .. you guys understand it as one master FSM controlling more than one slave FSMs .. Yet, I am asking about something different .. a case in which one upper state is encapsulating other lower states .. like a sphere that contains more than one smaller spheres inside it .

 

[pmat]

Re: Hierarchical FSM?

Check out Hierarchical task graphs (HTGs). A paper on such models, is
**broken link removed**
If i understand correctly these structures are the ones you are interested in. However
i have not seen any publications on RTL coding of such things. If it is possible,
provide me/us more details on what you are trying to implement...

Pavlos