PA Impedance matching

[Dummyeng]

I have question about designing impedance matching in PA RF transistor

In normal design like this https://www.nxp.com/docs/en/data-sheet/MRF13750H.pdf

i design for one line and then mirror it for another line (with Smith chart or other thing ) in the end it need only a little tune

But in this kind of design (https://www.wolfspeed.com/downloads/dl/file/id/1208/product/610/gtva101k42ev.pdf) how can I design it ?

Two gate and drain with power divider combine with each other and there are some cap that they are separated from each other like (c5 c12 c8 c9) but here (Iulian Rosu, YO3DAC / VA3IUL, https://www.qsl.net/va3iul/) it said in page 15 “Impedance Matching of Balanced Circuits” wecan series this kind of cap

i use below approach but it is very hard and need time. is there other way for impedance matching ?

I don’t need LoadPull (IN and OUT Transistor Impedance) and smith chart I only should put some ML in my design then try to tune them



And other question

First I use hybrid for MRF13750 in 900 1300MHz but it gets very large so I want to use divider

Is it useful to get my design smaller than before?

 

[Dummyeng]

i did it with tune and optimize without smithcart
but i have some problem
for example as you can see it isnt flat and i should try to tune it again. is it only way (tuning)?(without smith chart)
and you can see i face with a wierd err when i put alot of variable it comes up (when i want to optimize it)
first i want to make my amp balance(90 hybrid) but that was very big (i want two mrf parallel together for 1k)
and then i make it with divider and it only want two hybrid
i want to use microstrip hybrid is it practical or not?

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