As dick_freebird wrote, electrons in the inversion layer of a NMOS transistor are coming from source (and drain - depending on applied voltages) - if there are n+ source/drain regions abutting the gate.
In NMOS capacitor without n+ regions nearby, what happens when gate is biased positively is this - at first, holes are pulled away from the gate, a deep depletion region is formed under the gate, and thermal generation process in the depletion region generates electrons and holes. Holes are extracted by the built-in filed of the depletion region into the quasi-neutral substrate / well, while electrons are pulled to the gate and form an inversion layer. This process may be very slow (of the order of seconds or more) - if silicon is pure and if temperature is low (say -25C).
Max
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