P&E Decoder in Verilog

[eladla]

Hi,
I`m very new to HDLs, so please bare with me.

I want to design a dynamic decoder (precharge & evaluate).
The way I would do it in my analog designs is with a prechrge PMOS and discharge NMOS devices.
I was wondring if the same can be done with verilog.
I want to write behavioral code and synthesize a transistor level implementation.
I`m guessing this is not possible in tools designed for FPGAs,
but can this be done for ASICs, for instance?

If so, what tool can I use?

Thank you!

 

[lostinxlation]

You can manually code the netlist with Tr transistor primitives/cells. I don't think you can synthesize the transistor level design, let alone dynamic circuit, though I have seen the presentations that some companies had in-house tools to do transistor level synthesis.
The thing is no one uses dynamic circuits except for ultra high performance, and no company wants to invest on the market where only a handful of companies can be clients.

Behavioral model can probably be something like this(b = ((q0 & q1) | q2) where a, b, q* are all dynamic nodes).

tri0 a, b;

assign a = !clk ? 1'b0 :
               (q0 & q1) ? 1'b1 : 1'bz;
assign b = !clk ? 1'b0 :
               (a | q2) ? 1'b1 : 1'bz;

The best way is using 'tr' cells/primitives intead of behavioral model if you want to code the exact behaviors of dynamic circuits.