Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Output RMS jitter using pnoise analysis (Cadence)

Not open for further replies.


Member level 5
Jan 20, 2021
Reaction score
Trophy points
Activity points
Consider a chain of CMOS inverters connected in series. I want to know the output referred jitter because of the device noise, flicker noise and shot noise. The transient analysis is not suitable for this purpose as it does not consider all noise sources. So I tried to think about pnoise. There is however some ambiguity I ran into when trying to understand pnoise analysis for jitter measurement: According to my understanding, the simulator calculates output RMS jitter following this approach: At the instance the output voltage crosses the threshold voltage VDD/2, a noise analysis is performed. Having the noise profile one can integrate over the band to find RMS voltage noise. The RMS voltage noise then can be divided by the slew rate to arrive at the output RMS jitter. The thing I don't understand is whether the simulator considers the noise contribution from preceding inverters too? In other words, every inverter in the chain contributes to noise at its switching time, when gain is high, so jitter will be accumulated over the chain. Does pnoise analysis consider jitter accumulation in the output jitter calculation? How?

I think it's easy to convince yourself of a number from such
simulations but you need to know what is and isn't modeled.
The PNOISE I expect means it operates across a period. That
period must be set correctly for it to work at all. But things
which occur outside, or only occasionally inside, or "slide
through" (e.g. switching power supply overtones / impulses
that are asynchronous w.r.t. the signal of interest) would have
to be presented realistically, to have representation in the result.

That's your knock on the transient analysis; why is it any different
for this "transient plus behind-the-curtain-funny-business"?

If the preceding inverters are active within the period, then their
activity should pass through the base transient (one cycle)
analysis to the result.

PSS ties t find a periodic steady state operation of your circuit. Pnoise finds noise in that periodic steady state operating point i.e. over the period.
Yes, PNOISE takes into account noise from all devices and noise folding or noise translation around harmonics in the case of flicker noise.
You can do pretty much same thing also in transient analysis if you enable transient noise. You will have to set long enough simulation time to be able to capture also flicker noise effect and set the fmax for the transient noise to be able to capture thermal noise up to a sufficiently high frequencies.

Not open for further replies.

Part and Inventory Search

Welcome to