dirac16
Member level 5
Consider a chain of CMOS inverters connected in series. I want to know the output referred jitter because of the device noise, flicker noise and shot noise. The transient analysis is not suitable for this purpose as it does not consider all noise sources. So I tried to think about pnoise. There is however some ambiguity I ran into when trying to understand pnoise analysis for jitter measurement: According to my understanding, the simulator calculates output RMS jitter following this approach: At the instance the output voltage crosses the threshold voltage VDD/2, a noise analysis is performed. Having the noise profile one can integrate over the band to find RMS voltage noise. The RMS voltage noise then can be divided by the slew rate to arrive at the output RMS jitter. The thing I don't understand is whether the simulator considers the noise contribution from preceding inverters too? In other words, every inverter in the chain contributes to noise at its switching time, when gain is high, so jitter will be accumulated over the chain. Does pnoise analysis consider jitter accumulation in the output jitter calculation? How?