Output pin Inductance effect on Ground bounce

[tech_vlsi]

Please let me know whether by increasing Inductance value on SSO will effect the ground bounce or not(Inductance on POWER/GROUND REMAINS THE SAME).

 

[FvM]

Output inductance will reduce the current rise and fall time and thus can be expected to reduce ground bounce. At the same time it may cause other unwanted effects like output ringing and overshoot. Lowering drive strength or adding slew rate limitation as far as acceptable is the best way to reduce ground bounce (Presumed decreasing the ground inductance isn't an option).

 

[tech_vlsi]

Thanks for the reply.
In my design, output pin inductance (lead+trace+bonding wire) is 40nh and inductance on ground pin 2nh. What will be effect of this output pin inductance on my circuit behavior.

 

[FvM]

The problem is about SSO, so with a sufficient number of outputs switching simultaneously, you can still get ground bounce that exceeds locgic switching level.

 

[tech_vlsi]

Thanks for the reply.

Please correct me if my understanding is wrong.

In my design package parasitic inductance on output pins has been increased from 20nh to 40 nh. As this inductance is large as compared to ground inductance (2nh) current will be decided by larger inductance. So magnitude of ground bounce will reduce. But ringing on output pins will increase.

Is there anything more I need to take care in the design other than ringing.