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Output of XOR gate whose both inputs are "X"

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spartanthewarrior

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two input xor verilog code

Hi all,

What wil be the Output of XOR gate whose both inputs are "X".
 

bharat_in

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gating a digital output

if all the inputs are X, then output would always be X, no matter which gate it is
 

spartanthewarrior

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xor gate in verilog

output will be zero.

Added after 5 minutes:

output will be zero.

If you see XOR truth table whenever we have same inputs output is ZERO, So if both the inputs are X then output will be zero.
 

bharat_in

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xor gate german

Probably you haven't referred the verilog LRM. For your reference, I have attached a page from the LRM with this post.
Please, have a look at it. Your doubt will get clear after seeing the image.
 

trekkytekky

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how to get xor gates output

a catholic and a protestant can read the same bible and interpret it different ways.

Nothing was mentioned about verilog LRM.
If the question relates to verilog, bharat is right from his documentation.
On the other hand an eXclusive OR (XOR) will give a high output if and only if one input is high and not the other, so if the question is based on a generic 'X' as an unknown applied to both inputs then spartans is right.
 

spartanthewarrior

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vhdl code for xor gate

Thanks for the page but i think our realization of verilog code finally goes to digital logic. Which has some properties, so my understanding says. Whatever i mention above is rigth. Sorry for being so controversial and also for confusion.
 

bharat_in

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explanation of xor & x and gate

It's all right, spartan.

It's becoming interesting now, Even in real world we can not say for sure what will be the output.

See,
<Unknown> XOR "1" = <Opposite of Unknown>

<Unknown> XOR "0" = <Unknown>

So,
<Unknown> XOR <Unknown(which can be either 1 or 0)> = <Unknown or Opposite of Unknown... simply Unknown>

M not sure, but it seems right. What do u think??
 

mfarooq1

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2 and 1 or gate truth table xor gate verilog

In digital logic when input of a gate is X it is like high. and out put will be decided as the input is high. this high is very lose mean can give false results if your system is clocked for frequiencies above 1 MHZ.
 

FvM

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verilog codes for xor gates

In digital logic when input of a gate is X it is like high.
That's nonsense. You probably mean TTL logic family. That's not the same as digital logic. Also 'X' in HDL doesn't mean open circuit which is represented by 'Z'.

Regarding the original question: The recent explanation by bharat_in is the only one that's make sense. The above truth table must be expected to be valid for any digital logic.
 

trekkytekky

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xor inputs

<Unknown> XOR "1" = <Opposite of Unknown>

<Unknown> XOR "0" = <Unknown>

So,
<Unknown> XOR <Unknown(which can be either 1 or 0)> = <Unknown or Opposite of Unknown... simply Unknown>

If the _SAME_ unknown is applied to both inputs, the output is deterministic, not <Unknown>.
Assume Unknown is "1" or logic true, then "1" XOR "1" is ==>"0" or logic false
Assume Unknown is "0" or logic false, then "0" XOR "0" is =>"0" or logic false
irrespective of the unknown, the output is determined.

However, if X relates to two _DIFFERENT_ unknowns, then all bets are off.

Reading the original it appeared the same input applied to both inputs.
 

FvM

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xor verilog truth table

Reading the original it appeared the same input applied to both inputs.
I don't see an indication for this assumption.

Furthermore, in simulation, the tool possibly won't be aware that both XOR input signals are identical, because it may interprete the logic rather than minimizing it before simulation.

In HDL synthesis, the tool will replace signal_a XOR signal_a by a constant '0'. In this trivial case, the output won't be different by assigning 'X' to signal_a.
 

haneet

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xor gate output

guyz...
I agree with what FvM said. A simple logic...

we should understand one thing that X may be a '0' or '1'. when we say X to two pints the6y need not be holding the same value. It may be same or different so which concludes as bharat said the output as 'X'.
However if you consider the same case with both input's as 'Z' then i wld go with the answer give by spartan.

haneet
 

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