Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Output of D flip flop with input and clk pin shorted

Prameeth

Newbie
Joined
Aug 3, 2020
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
51
My query is when the clk pin is shorted to the input pin(Din) of d flip flop, will the output be zero or undefined? My understanding is when the clk is shorted to input as well, then there will be hold timing violation resulting in undefined output. Please correct me if I'm wrong.
Thank you
 

danadakk

Advanced Member level 1
Joined
Mar 26, 2018
Messages
404
Helped
79
Reputation
157
Reaction score
89
Trophy points
28
Activity points
2,046

BradtheRad

Super Moderator
Staff member
Joined
Apr 1, 2011
Messages
13,643
Helped
2,700
Reputation
5,396
Reaction score
2,618
Trophy points
1,393
Location
Minneapolis, Minnesota, USA
Activity points
101,880
clk pin is shorted to the input pin(Din) of d flip flop
D FF inputs need to receive definite high or low value at startup and running. (As do all digital IC's).

Simply connecting inputs together is equivalent to leaving inputs floating which is not recommended. It can result in unpredictable behavior.

A D FF can receive any combination of hi or low voltage at input pins, once you achieve stable running.
 

dick_freebird

Advanced Member level 5
Joined
Mar 4, 2008
Messages
6,909
Helped
2,023
Reputation
4,050
Reaction score
1,862
Trophy points
1,393
Location
USA
Activity points
55,333
It depends which side of the setup time the
D transition (= CLK) lies. At tsetup>0 the output
will be 0 for a positive edge triggered 'flop (or
1 for a negative edge triggered.

For tsetup=0 the output will be undefined /
metastable.

Tsetup < 0 is abnormal in my experience.
 

danadakk

Advanced Member level 1
Joined
Mar 26, 2018
Messages
404
Helped
79
Reputation
157
Reaction score
89
Trophy points
28
Activity points
2,046
Decent description of D -



Regards, Dana.
 

Prameeth

Newbie
Joined
Aug 3, 2020
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
51
Thanks a lot for the answers. I get the idea for the positive edge trig flop. But then, wouldn't there be only hold violation and not setup violation (assuming positive library setup and hold times of flop). Because anyway the clk which is the input is settled at Din(constant and not changing) at the active edge (rising edge in this case). But because the value at Din immediately changes after the positive edge, hold violation occurs. And hence output becomes unpredictable. Please correct me if I am wrong. Thank you.
 

dick_freebird

Advanced Member level 5
Joined
Mar 4, 2008
Messages
6,909
Helped
2,023
Reputation
4,050
Reaction score
1,862
Trophy points
1,393
Location
USA
Activity points
55,333
It all depends on those details. If you had a
transistor level DFF circuit netlist you could
simulate the real goings-on and understand.
Looking at "datasheet" numbers, sandbagged
as they tend to be, may be a source of some
confusion.
 

BradtheRad

Super Moderator
Staff member
Joined
Apr 1, 2011
Messages
13,643
Helped
2,700
Reputation
5,396
Reaction score
2,618
Trophy points
1,393
Location
Minneapolis, Minnesota, USA
Activity points
101,880
Simulation of edge-triggered D flip-flop, with incoming pulses applied to both clock and D input simultaneously.

The result is erratic behavior, apparently because disallowed states occur. Flickering is seen among the branches connecting the NAND gates. (Green= high, gray= low). The left half of the circuit is stable only when inputs are low.

(Schematic is a spin-off of the model found in the Circuits menu of Falstad's animated simulator.)
edge-triggered D flip-flop (joined inputs cause erratic output).png
 

dick_freebird

Advanced Member level 5
Joined
Mar 4, 2008
Messages
6,909
Helped
2,023
Reputation
4,050
Reaction score
1,862
Trophy points
1,393
Location
USA
Activity points
55,333
Structural veriloga has this problem if the gates
don't each have a finite delay. That's key to the
master-slave handoff. If everything has zero
delay then it all tries to happen at once (and
good luck with that - turns relay race into a
mosh pit).
 

Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top