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output impendence of CMOS

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Full Member level 6
Mar 28, 2006
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i want to ask that what is the output impendence of CMOS on power off condition.

problem is that i connected two buffer out together one on at one time so if one buffer on the off buffer started to sink the currrent.

i am using CMOS output buffers

please help me in this regard


What you mean CMOS buffer. Does it has high impedance in OFF state?

i am using 74ACT245 having CMOs output...

i want to ask, typically what is the output impeadence of CMOS circuit during off state.

CMOS has 2 FET's in the output, one P-FET and one N-FET. When both are off there is a high impedance off state. When the P-FET is conducting you see the Vdd (+V) value on the output. When the N-FET is conducting you see the Vss (Gnd) value on the output.

So when the CMOS output is logical 0, its really at Vss or Ground. This a current sink for some circuits. When your output is logical 1, it's at Vdd level or +V of the device. This is a current source state for some circuits.

If your CMOS device does not have a high-impedance control pin then your CMOS output will be at +V or Ground at all times. Typically, this is a couple hundred ohms. See these notes by Texas Instruments:

I see that the device you listed has 3-state capability but the datasheet does not give much detail about how much impedance is high-impedance. This might be available in another datasheet or CMOS reference.

I found it.... it's Ioz = 5.5V/5uA = 1.1Mohms. This is the mimimum impedance and can be more. Another datasheet shows 2.2Mohms.

Here is some helpful information when connecting 3-state devices:
**broken link removed**

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