Output comes after few clock cycle

[sarjumaharaj]

This is a program for shift register. I've used datapath and controller method to design the circuit. I got the output but the output comes after a delay. What could possibly be the error.

Here:
c0 c1
0 0 HOLD
0 1 SHIFT RIGHT
1 0 SHIFT LEFT
1 1 PARALLEL LOAD

sl sr pl : signals to shift left shift right and parallel load. If all the signals are 0 then the datapath should hold the data.

sli/sil -> serial input left ;
sri/sir -> serial input right ;
pil/pli -> parallel load input

One more thing I haven't you states for the controller just if statements. Could that be the reason for the output to be irratic. Both the comonents work fine individually. (i checked). If that's the reason can you explain why it is so?
MAIN MODULE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity mainmoduleexam is
	port (clk , c0 , c1 , start : in std_logic ;
			pli : in std_logic_vector (4 downto 1); 
			sli, sri : in std_logic ;
			po: out std_logic_vector (4 downto 1)
			); 
			
end mainmoduleexam;

architecture Behavioral of mainmoduleexam is


component datapath is
	port (clk , sl , sr, pl : in std_logic ;
			 sil , sir : in std_logic ;
			 pli: in std_logic_vector (4 downto 1); 
			 pl0: out std_logic_vector (4 downto 1 ) 
		  );
			 
end component;


component controller is
	port (clk , start , c0 ,c1  : in std_logic ;
			sl, sr , pl : out std_logic ); 
end component;

signal s_sl , s_sr , s_pl  : std_logic ;
begin

data : datapath port map(clk , s_sl , s_sr , s_pl , sli , sri , pli  , po); 
control : controller port map ( clk,start , c0 ,c1, s_sl , s_sr , s_pl ) ; 

end Behavioral;

CONTROLLER:

library ieee; 
use IEEE.STD_LOGIC_1164.ALL;

entity controller is
	port (clk , start , c0 ,c1  : in std_logic ;
			sl, sr , pl : out std_logic ); 
end controller;

architecture Behavioral of controller is

begin

process (clk ) 
begin 
if  (start ='0') then
		sl <='0' ; 
		sr <= '0' ; 
		pl <= '0'; 
elsif(rising_edge (clk ) and start ='1' ) then 
	if (c0 = '0' and c1 = '0' )then 
		sl <='0' ; 
		sr <= '0' ; 
		pl <= '0'; 
	elsif (c0 ='1' and c1 = '0' ) then 
		sl <='1'; 
		sr <='0';
		pl <='0'; 
	elsif (c0 = '0' and c1 = '1' ) then 
		sl <='0';
		sr <='1'; 
		pl <='0'; 
	elsif (c0 = '1' and c1 ='1' ) then 
		sl <='0';
		sr <='0';
		pl <= '1' ; 
	end if ; 
	
end if ; 
end process ;
end Behavioral;

DATAPATH:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity datapath is
	port (clk , sl , sr, pl : in std_logic ;
			 sil , sir : in std_logic ;
			 pli: in std_logic_vector (4 downto 1); 
			 pl0: out std_logic_vector (4 downto 1 ) 
		  );
			 
end datapath;

architecture Behavioral of datapath is


begin
process (clk )

variable memory : std_logic_vector (4 downto 1 ):= "0000" ;
begin 
if (rising_edge (clk)) then


	if (sl ='0' and sr = '0' and pl ='0' ) then 
		for i in 1 to 4 loop
			memory(i) := memory(i); 
		end loop;
		
	elsif (sl = '1' ) then 
		for i in 4 downto 2 loop 
			memory(i) := memory (i -1 );
		end loop ; 
		memory(1) := sil ;
		
	elsif ( sr = '1' ) then 
		for i in 1 to 3 loop
			memory(i) :=memory (i +1);
		end loop;
		memory (4) := sir ; 
		
	elsif ( pl = '1' ) then 
		memory := pli  ;
	end if ;


pl0 <= memory ; 
end if ; 

end process ;
end Behavioral;

OUTPUT

 

[layowblue]

Hi sarjumaharaj

It is not difficult to debug given you've loaded up your simulation as attached.
I spent two minutes to find the issue. But I would really prefer that you debug yourself first for a while before you ask this question. You are so close to the solution.

After putting more effort and if you still can't get it, reply this post again and I'll point it out.

Also, I highly recommend you follow some basic coding style like denting, single-line declaration for a signal, etc.